diff options
| author |  homunkulus <homunkulus@gmx.com>
| 2018-01-11 14:48:44 +0000 |
|---|---|---|
| committer | homunkulus <homunkulus@gmx.com>
| 2018-01-11 14:48:44 +0000 |
| commit | 34f662106f327c25d00733773492cf80e9a4804a (patch) | |
| tree | fb16dc095967377caef65a79d3d9f312e57b714a /src | |
| parent | 6a5a789b60f88c50bb8712fd35dfcb3339018cb0 (diff) | |
| parent | f6ee6d0c49a5b87a51385dad625b372a4870d34d (diff) | |
| download | cortex-m-34f662106f327c25d00733773492cf80e9a4804a.tar.gz cortex-m-34f662106f327c25d00733773492cf80e9a4804a.tar.zst cortex-m-34f662106f327c25d00733773492cf80e9a4804a.zip | |
Auto merge of #72 - japaric:cm7-r0p1, r=japaric
add a Cargo feature, cm7-r0p1, to fix a Cortex-M7 BASEPRI erratum
see japaric/cortex-m-rtfm#53 for background information
Diffstat (limited to 'src')
| -rw-r--r-- | src/register/basepri.rs | 15 | ||||
| -rw-r--r-- | src/register/basepri_max.rs | 15 |
2 files changed, 26 insertions, 4 deletions
diff --git a/src/register/basepri.rs b/src/register/basepri.rs index a024d74..c9be9d3 100644 --- a/src/register/basepri.rs +++ b/src/register/basepri.rs @@ -18,11 +18,22 @@ pub fn read() -> u8 { } /// Writes to the CPU register +/// +/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the +/// `cm7-r0p1` Cargo feature or this function WILL misbehave. +#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))] #[inline] -pub unsafe fn write(_basepri: u8) { +pub unsafe fn write(basepri: u8) { match () { #[cfg(target_arch = "arm")] - () => asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"), + () => match () { + #[cfg(not(feature = "cm7-r0p1"))] + () => asm!("msr BASEPRI, $0" :: "r"(basepri) : "memory" : "volatile"), + #[cfg(feature = "cm7-r0p1")] + () => asm!("cpsid i + msr BASEPRI, $0 + cpsie i" :: "r"(basepri) : "memory" : "volatile"), + }, #[cfg(not(target_arch = "arm"))] () => unimplemented!(), } diff --git a/src/register/basepri_max.rs b/src/register/basepri_max.rs index 0833aa7..c386e86 100644 --- a/src/register/basepri_max.rs +++ b/src/register/basepri_max.rs @@ -4,12 +4,23 @@ /// /// - `basepri != 0` AND `basepri::read() == 0`, OR /// - `basepri != 0` AND `basepri < basepri::read()` +/// +/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the +/// `cm7-r0p1` Cargo feature or this function WILL misbehave. +#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))] #[inline] -pub fn write(_basepri: u8) { +pub fn write(basepri: u8) { match () { #[cfg(target_arch = "arm")] () => unsafe { - asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile"); + match () { + #[cfg(not(feature = "cm7-r0p1"))] + () => asm!("msr BASEPRI_MAX, $0" :: "r"(basepri) : "memory" : "volatile"), + #[cfg(feature = "cm7-r0p1")] + () => asm!("cpsid i + msr BASEPRI_MAX, $0 + cpsie i" :: "r"(basepri) : "memory" : "volatile"), + } }, #[cfg(not(target_arch = "arm"))] () => unimplemented!(), |