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| author |  Jorge Aparicio <jorge@japaric.io>
| 2017-06-30 12:23:39 -0500 |
|---|---|---|
| committer | Jorge Aparicio <jorge@japaric.io>
| 2017-06-30 12:23:39 -0500 |
| commit | 58b53670ca6a27c0a7007068f0886330ca448de8 (patch) | |
| tree | 72f7bc3d75e1c4d19eb510c9c57a704fe1fb1626 /src | |
| parent | c0e7dcb9334e735040d7a7e1c3f44cadc61fec73 (diff) | |
| download | cortex-m-58b53670ca6a27c0a7007068f0886330ca448de8.tar.gz cortex-m-58b53670ca6a27c0a7007068f0886330ca448de8.tar.zst cortex-m-58b53670ca6a27c0a7007068f0886330ca448de8.zip | |
unbreak test
Diffstat (limited to 'src')
| -rw-r--r-- | src/peripheral/mod.rs | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs index e210c79..7750c47 100644 --- a/src/peripheral/mod.rs +++ b/src/peripheral/mod.rs @@ -104,16 +104,16 @@ pub struct Cpuid { pub isar: [RO<u32>; 5], reserved1: u32, /// Cache Level ID - #[cfg(armv7m)] + #[cfg(any(armv7m, test))] pub clidr: RO<u32>, /// Cache Type - #[cfg(armv7m)] + #[cfg(any(armv7m, test))] pub ctr: RO<u32>, /// Cache Size ID - #[cfg(armv7m)] + #[cfg(any(armv7m, test))] pub ccsidr: RO<u32>, /// Cache Size Selection - #[cfg(armv7m)] + #[cfg(any(armv7m, test))] pub csselr: RW<u32>, } |