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| author |  Jorge Aparicio <jorge@japaric.io>
| 2018-05-11 18:08:36 +0200 |
|---|---|---|
| committer | Jorge Aparicio <jorge@japaric.io>
| 2018-05-11 18:08:36 +0200 |
| commit | 716398ce542798aff238abc6a978d3b64a1c0dd4 (patch) | |
| tree | 6d8ae571f039002e5571755a58ecead2b6b653a1 /src | |
| parent | 1d6864377202bc64e522deeb5dd044e593d83ebb (diff) | |
| download | cortex-m-716398ce542798aff238abc6a978d3b64a1c0dd4.tar.gz cortex-m-716398ce542798aff238abc6a978d3b64a1c0dd4.tar.zst cortex-m-716398ce542798aff238abc6a978d3b64a1c0dd4.zip | |
fix build on ARMv6-M
Diffstat (limited to 'src')
| -rw-r--r-- | src/peripheral/scb.rs | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 70144c1..e31c902 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -9,7 +9,8 @@ use super::cpuid::CsselrCacheType; #[cfg(any(armv7m, target_arch = "x86_64"))] use super::CPUID; #[cfg(any(armv7m, has_fpu, target_arch = "x86_64"))] -use super::{CBP, SCB}; +use super::CBP; +use super::SCB; /// Register block #[repr(C)] |