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| author |  Brandon Matthews <bmatthews@optimaltour.us>
| 2019-03-12 14:20:56 -0700 |
|---|---|---|
| committer | Brandon Matthews <bmatthews@optimaltour.us>
| 2019-03-12 14:20:56 -0700 |
| commit | 771fc84d6ea9d669848baf6acff9e54b36819eb1 (patch) | |
| tree | 11b830f40374fd665a77b25277ecc380ba30ea69 /src | |
| parent | 2ff4735cda7d5cce9bdff8ac5ec7576998f007a1 (diff) | |
| download | cortex-m-771fc84d6ea9d669848baf6acff9e54b36819eb1.tar.gz cortex-m-771fc84d6ea9d669848baf6acff9e54b36819eb1.tar.zst cortex-m-771fc84d6ea9d669848baf6acff9e54b36819eb1.zip | |
Fix STIR register test, remove armv6m-related offsets in NVIC
Diffstat (limited to 'src')
| -rw-r--r-- | src/peripheral/nvic.rs | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs index a81fa6d..57ce009 100644 --- a/src/peripheral/nvic.rs +++ b/src/peripheral/nvic.rs @@ -1,8 +1,8 @@ //! Nested Vector Interrupt Controller +use volatile_register::RW; #[cfg(not(armv6m))] use volatile_register::{RO, WO}; -use volatile_register::RW; use interrupt::Nr; use peripheral::NVIC; @@ -67,10 +67,7 @@ pub struct RegisterBlock { pub ipr: [RW<u32>; 8], #[cfg(not(armv6m))] - reserved5: [u32; 208], - - #[cfg(armv6m)] - reserved5: [u32; 696], + _reserved6: [u32; 580], #[cfg(not(armv6m))] /// Software Trigger Interrupt |