3 files changed, 100 insertions, 0 deletions
diff --git a/src/register/mod.rs b/src/register/mod.rs
index 1444aff..854d725 100644
--- a/src/register/mod.rs
+++ b/src/register/mod.rs
@@ -43,6 +43,12 @@ pub mod primask;
 
 pub mod psp;
 
+#[cfg(armv8m_main)]
+pub mod msplim;
+
+#[cfg(armv8m_main)]
+pub mod psplim;
+
 // Accessing these registers requires inline assembly because their contents are tied to the current
 // stack frame
 #[cfg(any(feature = "inline-asm", target_arch = "x86_64"))]
diff --git a/src/register/msplim.rs b/src/register/msplim.rs
new file mode 100644
index 0000000..df3642a
--- /dev/null
+++ b/src/register/msplim.rs
@@ -0,0 +1,47 @@
+//! Main Stack Pointer Limit Register
+
+/// Reads the CPU register
+#[inline]
+pub fn read() -> u32 {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => {
+            let r;
+            unsafe { asm!("mrs $0,MSPLIM" : "=r"(r) ::: "volatile") }
+            r
+        }
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __msplim_r() -> u32;
+            }
+
+            __msplim_r()
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Writes `bits` to the CPU register
+#[inline]
+pub unsafe fn write(_bits: u32) {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => asm!("msr MSPLIM,$0" :: "r"(_bits) :: "volatile"),
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => {
+            extern "C" {
+                fn __msplim_w(_: u32);
+            }
+
+            __msplim_w(_bits);
+        }
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
diff --git a/src/register/psplim.rs b/src/register/psplim.rs
new file mode 100644
index 0000000..6c27008
--- /dev/null
+++ b/src/register/psplim.rs
@@ -0,0 +1,47 @@
+//! Process Stack Pointer Limit Register
+
+/// Reads the CPU register
+#[inline]
+pub fn read() -> u32 {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => {
+            let r;
+            unsafe { asm!("mrs $0,PSPLIM" : "=r"(r) ::: "volatile") }
+            r
+        }
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __psplim_r() -> u32;
+            }
+
+            __psplim_r()
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Writes `bits` to the CPU register
+#[inline]
+pub unsafe fn write(_bits: u32) {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => asm!("msr PSPLIM,$0" :: "r"(_bits) :: "volatile"),
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => {
+            extern "C" {
+                fn __psplim_w(_: u32);
+            }
+
+            __psplim_w(_bits);
+        }
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}