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2020-10-13Import semihosting crates as-isGravatar Jonas Schievink 45-0/+1954
2020-10-02Merge #268Gravatar bors[bot] 18-0/+49
268: Add some Armv8-M assembly routines r=jonas-schievink a=hug-dev Adds access to `MSP_NS` and the `BXNS` instruction. Also adds `__dsb` which was missing. Executed `cargo xtask assemble` and pushed everything, I hope that's enough. Co-authored-by: Hugues de Valon <hugues.devalon@arm.com>
2020-10-02Add some Armv8-M assembly routinesGravatar Hugues de Valon 18-0/+49
Adds access to MSP_NS and the BXNS instruction. Also adds __dsb which was missing. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-09-21Merge #266Gravatar bors[bot] 2-1/+12
266: Implement InterruptNumber for bare_metal::Nr r=therealprof a=adamgreig This PR aims to help backwards compatibility by implementing the new `InterruptNumber` trait (coming in cortex-m 0.7) for the old `bare_metal::Nr` trait. With this included in cortex-m 0.7, existing PACs generated from the current svd2rust (0.17) will work with cortex-m 0.7, and new PACs generated from a to-be-released svd2rust which uses `InterruptNumber directly will also work. We can then remove this implementation in cortex-m 0.8 and upgrade cortex-m to depend on bare-metal 1.0 (or not depend on it at all) at that time. With this PR in place, the upgrade path looks like: * We release cortex-m 0.7, which users can upgrade to without needing a new PAC * We release svd2rust 0.18, which will generate new PACs * PACs update, now requiring cortex-m 0.7 * Users can update their PAC so long as they've already upgraded to cortex-m 0.7 * For cortex-m 0.8, we drop this impl and move off bare-metal 0.2, and a new PAC is required to use 0.8 onwards Co-authored-by: Adam Greig <adam@adamgreig.com>
2020-09-22Update CHANGELOG for InterruptNumber impl for NrGravatar Adam Greig 1-0/+2
2020-09-20Implement InterruptNumber for bare_metal::NrGravatar Adam Greig 1-1/+10
2020-09-15Merge #264Gravatar bors[bot] 16-66/+91
264: Tidy up some inline asm and add compiler fences where appropriate r=therealprof a=adamgreig This PR updates the inline asm: * Use compiler-assigned registers instead of specifying r0/r1/r2 * Write multi-line asm as multiple string literals, with normal Rust comments outside the strings * Add ISB after writing to CONTROL as per ARM architectural requirements (see eg app note 321). As far as I can see no other requirements from AN321 apply here. * Add compiler fences around enabling and disabling interrupts * No runtime barriers are required, but the compiler fences ensure the compiler won't reorder instructions around these operations, which would break critical section soundness. * Add compiler fences around DMB, DSB, ISB to align compiler behaviour with the barrier runtime behaviour. * Add compiler fences after the cache enable routines and writing to CONTROL since those routines include an ISB instruction. Open to feedback on whether more or fewer fences are necessary; I've thought about these a bit but I think it's a tricky subject. I think in general the FFI-esque treatment of the new `asm!` block probably does most of what we need, but I'm told LLVM may still reorder instructions around FFI calls, which we really don't want to happen here. Co-authored-by: Adam Greig <adam@adamgreig.com> Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-09-11Update blobsGravatar Jonas Schievink 14-0/+0
2020-09-05Add note about LTO inlining assembly to CHANGELOGGravatar Adam Greig 1-0/+2
2020-09-05Address review commentsGravatar Adam Greig 2-5/+18
2020-09-03Tidy up some inline asm and add compiler fences where appropriateGravatar Adam Greig 15-66/+76
2020-08-31Merge #262Gravatar bors[bot] 39-1105/+704
262: Merge asm implementations r=therealprof a=jonas-schievink This replaces the implementation of `inline-asm` with the file I wrote in #259 (and some fixes). All functions that call assembly now do so via a `call_asm!` macro that either dispatches to a call to an `#[inline(always)]` function containing the inline `asm!`, or to the FFI shim. This makes all functions that call into asm significantly shorter. The FFI shim is now also macro-generated, which makes it very small. Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-08-31Update documented MSRVGravatar Jonas Schievink 2-2/+2
2020-08-30Bump MSRV to 1.38.0Gravatar Jonas Schievink 1-1/+1
2020-08-30Patch out the asm shim panic handlerGravatar Jonas Schievink 9-2/+97
2020-08-29Delete old asm.rsGravatar Jonas Schievink 1-346/+0
2020-08-29Fix shims for v8m.mainGravatar Jonas Schievink 15-1/+2
2020-08-29Merge #258Gravatar bors[bot] 1-1/+19
258: changelog: forward-port 0.6.3 release notes r=adamgreig a=jonas-schievink Fixes https://github.com/rust-embedded/cortex-m/issues/252 Co-authored-by: Adam Greig <adam@adamgreig.com>
2020-08-29Merge asm implementationsGravatar Jonas Schievink 35-754/+603
2020-08-28Merge #261Gravatar bors[bot] 7-331/+284
261: Replace shell scripts with integration test r=therealprof a=jonas-schievink * Removes the Clippy check from CI (I don't think we should fail CI when Clippy finds something, it seems better to use the GitHub Actions plugin) * Tests all targets (thumbv8m.base was missing) * Bumps MSRV to 1.35.0 (to get the thumbv8m.base libcore) Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-08-28Replace shell scripts with integration testGravatar Jonas Schievink 7-331/+284
2020-08-27Merge #259Gravatar bors[bot] 33-492/+619
259: Rust assembly stubs r=thalesfragoso a=jonas-schievink Disclaimer: I have not tested any of this (help wanted, we have no tests in here). Thanks to @therealprof for nerd-sniping me into oblivion. Fixes https://github.com/rust-embedded/cortex-m/issues/254 Fixes https://github.com/rust-embedded/cortex-m/issues/194 Fixes https://github.com/rust-embedded/cortex-m/issues/139 # Summary * Remove the assembly files in favor of a new `asm.rs`, which uses unstable inline assembly and provides a C ABI interface. * Replace the shell scripts by a [`cargo-xtask`](https://github.com/matklad/cargo-xtask/). * While we're at it, also pre-build artifacts that are compatible with linker-plugin LTO, fixing https://github.com/rust-embedded/cortex-m/issues/139 (again, not tested) This means that contributors and maintainers just need ~~a nightly Rust compiler installed~~ to run `cargo xtask assemble`. No binutils, no assembler, no `ar`, no GCC/Clang, and especially nothing from the godawful Arm servers, fixing https://github.com/rust-embedded/cortex-m/issues/194. You don't even have to install the correct nightly Rust toolchain, `cargo xtask` does it for you (and installs all the thumb targets too). Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-08-27Merge #260Gravatar bors[bot] 2-3/+3
260: Remove outdated TODO r=therealprof a=jonas-schievink STIR has been wrapped in the NVIC (it isn't standalone) Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-08-27Remove outdated TODOGravatar Jonas Schievink 2-3/+3
2020-08-27Move feature docs to lib.rs and improve themGravatar Jonas Schievink 2-5/+26
2020-08-26automate, automateGravatar Jonas Schievink 18-16/+49
2020-08-26Only check blobs with the nightly compilerGravatar Jonas Schievink 1-0/+13
2020-08-26Rust assembly stubsGravatar Jonas Schievink 31-492/+552
2020-08-25Merge #257Gravatar bors[bot] 5-0/+126
257: Provide a delay driver based on SysTick r=thalesfragoso a=Disasm Co-authored-by: Vadim Kaushan <admin@disasm.info>
2020-08-25changelog: forward-port 0.6.3 release notesGravatar Adam Greig 1-1/+19
2020-08-25Moar full stops.Gravatar Vadim Kaushan 1-4/+4
2020-08-24Add preludeGravatar Vadim Kaushan 2-0/+4
2020-08-24Update src/delay.rsGravatar Vadim Kaushan 1-1/+1
Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-08-23Add change log entryGravatar Vadim Kaushan 1-0/+1
2020-08-23Provide a delay driver based on SysTickGravatar Vadim Kaushan 3-0/+121
2020-08-23Merge #256Gravatar bors[bot] 1-0/+11
256: Add embedded targets to docs.rs r=jonas-schievink a=hug-dev Some modules of this repo are gated by the various targets and hence docs.rs does not show the documentation for them! Like the Armv8-M ones for [example](https://github.com/rust-embedded/cortex-m/issues/217#issuecomment-661039292) and the `cmse` module. docs.rs now allows building for specific target and since [this PR](https://github.com/rust-lang/docs.rs/pull/633) even for targets available via `rustup`! The `stm32f3_discovery` crate does it, look at ["Platform" on docs.rs](https://docs.rs/stm32f3-discovery/0.4.0/stm32f3_discovery/index.html). So I think it would be very neat to have on `cortex-m` and I proposing to add the following targets. The first one will show by default, I choosed the latest and greatest for that 😄 I tested locally with `cargo doc --target ...` for all of them. Co-authored-by: Hugues de Valon <hugues.devalon@arm.com>
2020-08-23Add embedded targets to docs.rsGravatar Hugues de Valon 1-0/+11
Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-08-18Merge #255Gravatar bors[bot] 8-14/+17
255: Remap debuginfo paths r=therealprof a=jonas-schievink cc https://github.com/rust-embedded/cortex-m/issues/254 Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-08-18Remap debuginfo pathsGravatar Jonas Schievink 8-14/+17
2020-07-28Merge #235Gravatar bors[bot] 2-59/+103
235: make 'fn ptr()' APIs to be 'const fn ptr()' r=therealprof a=JOE1994 This PR changes functions like `ITM::ptr()`, `DWT::ptr()` to become `const fn`s. * functions like `ITM::ptr()`, `DWT::ptr()` return pointers that are cast from constants, but currently these functions can't be used to define a constant. This PR will allow below code to compile. ```rust use cortex_m::peripheral::ITM; use cortex_m::peripheral::itm::RegisterBlock; // Below line currently won't compile, since `ITM::ptr()` is not a `const fn` const ITM_PTR: *mut RegisterBlock = ITM::ptr(); ``` I couldn't think of disadvantages that might accompany this change, but please correct me if I'm wrong. Thank you for reviewing this PR :+1: Co-authored-by: JOE1994 <joseph942010@gmail.com> Co-authored-by: Youngsuk Kim <joseph942010@gmail.com>
2020-07-27Update CHANGELOG.mdGravatar Youngsuk Kim 1-2/+1
Co-authored-by: Daniel Egger <daniel@eggers-club.de>
2020-07-27CHANGELOG: const 'PTR' is introduced for Core PeripheralsGravatar JOE1994 1-0/+3
2020-07-27Peipheral deref/ptr APIs now use associated const PTRGravatar JOE1994 1-30/+30
2020-07-27rename associated consts to 'PTR'Gravatar JOE1994 1-14/+14
2020-07-27add ptr to registerblock as associated constantGravatar JOE1994 1-14/+56
This commit introduces new associated constants to Core Peripherals. (pointers to the register block) This commit also adds a notice that 'ptr()' APIs will be deprecated in v0.7.
2020-07-27make 'fn ptr()' APIs to be 'const fn ptr()'Gravatar JOE1994 1-15/+15
2020-07-22Merge #241Gravatar bors[bot] 3-34/+58
241: Add new InterruptNumber trait r=therealprof a=adamgreig This is a first go at the new trait needed for https://github.com/rust-embedded/svd2rust/pull/455 since we removed `Nr` from bare-metal. In this case I've written it as `unsafe trait InterruptNumber: Into<u16>` rather than providing a conversion method inside the trait; I think this is neat and idiomatic but please correct me if there's a reason to not do it like this. [Here's](https://play.rust-lang.org/?version=stable&mode=debug&edition=2018&gist=4f2f8b9604b5a62298f9907780d844c7) a playground link showing an example implementation. Co-authored-by: Adam Greig <adam@adamgreig.com>
2020-07-22Merge #251Gravatar bors[bot] 2-3/+5
251: Fix warnings r=therealprof a=thalesfragoso This was causing CI to fail when using `-D warnings`. Co-authored-by: Thales Fragoso <thales.fragosoz@gmail.com>
2020-07-21please clippyGravatar Thales Fragoso 1-2/+2
2020-07-21Remove unused import in thumbv6Gravatar Thales Fragoso 1-1/+3
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