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2022-02-24Bump to Edition 2021 and rust-version 1.59Gravatar Adam Greig 2-2/+4
2022-02-24Remove references to unsupported Rust versions in cortex-m-rtGravatar Adam Greig 1-40/+9
2022-02-24Add set-sp and set-vtor features to cortex-m-rt.Gravatar Adam Greig 3-0/+37
2022-02-24Remove prebuilt cortex-m-rt binaries, replace with global_asmGravatar Adam Greig 15-183/+130
2022-02-24Allow #[naked] attribute on interrupt handlers and pre_initGravatar Adam Greig 1-0/+1
2022-01-26c-m-rt: fix macro hygiene, set to edition 2018Gravatar Adam Greig 2-2/+3
2022-01-26Fix #414Gravatar Adam Greig 2-1/+12
Partially reverts https://github.com/rust-embedded/cortex-m-rt/pull/224 to continue to use a fully-qualified path to `exception`.
2022-01-23Bump MSRV from 1.40 to 1.42, fix clippy::match_like_matches_macroGravatar Alex Martens 3-10/+4
2022-01-23Fix most clippy lintsGravatar Alex Martens 1-3/+3
2022-01-21Fix break in compilefail tests on 1.58Gravatar Adam Greig 1-2/+4
2022-01-12Move device.x example to workspace root for cortex-m-rt tests.Gravatar Adam Greig 1-3/+0
2022-01-12Fix cortex-m-rt build that was depending on old cortex-m via out-of-tree ↵Gravatar Adam Greig 1-1/+1
cortex-m-semihosting
2022-01-12Fix cortex-m-rt compiletest testsGravatar Adam Greig 3-7/+4
2022-01-12Move examples' memory.x to workspace rootGravatar Adam Greig 1-23/+0
2022-01-12Bump cortex-m-rt MSRV 1.39->1.40 to support non_exhaustive in cortex-mGravatar Adam Greig 2-2/+2
2022-01-12Update GHA for integrated cortex-m-rtGravatar Adam Greig 8-141/+3
2021-11-24Add/update links.Gravatar Jonathan Pallant (Ferrous Systems) 1-1/+2
2021-11-24Update to 0.7.1.Gravatar Jonathan Pallant (Ferrous Systems) 2-1/+9
2021-11-23Add commentGravatar Jonas Schievink 1-0/+4
2021-11-22Preserve `lr` and add debuginfoGravatar Jonas Schievink 8-0/+4
2021-11-22Assemble with debuginfoGravatar Jonas Schievink 1-7/+7
2021-11-22Rerun build script when archive changesGravatar Jonas Schievink 1-5/+3
Fixes https://github.com/rust-embedded/cortex-m-rt/issues/236
2021-08-19Fix links in CHANGELOG.mdGravatar Matt Ickstadt 1-9/+9
2021-08-17Fix CHANGELOG for recent 0.7 release.Gravatar Adam Greig 1-1/+4
2021-07-13Only run tests on stable and nightly, not MSRV.Gravatar Adam Greig 1-1/+4
2021-07-12Prepare for v0.7.0Gravatar Adam Greig 3-9/+59
2021-04-29bump version to 0.6.13Gravatar Robert Jördens 1-1/+1
The currently released version is 0.6.13 but the version in Cargo.toml was still 0.6.11. This enables cargo-patching in the git repository if other crates need newer cortex-m-rt.
2021-04-07link.x.in: move sgstubs after dataGravatar Robert Jördens 1-13/+13
2021-04-07link.x.in: put most __[se] symbols back into sectionsGravatar Robert Jördens 1-18/+27
This puts most start/end address symbols back into the sections. Only `__ebss` and `__edata` are kept outside their sections so that potential user code with external libraries can inject stuff using `INSERT AFTER .bss/.data` and profit from the .bss/.data zeroing/loading mechanism. This also leads to the `__sbss` and `__veneer_base` symbols having the right section type (B not D in nm). Also the trust zone start and end address are aligned to 32 bytes as per the requirements. That section does cost up to 28 byte of FLASH due to that alignment even if empty. The .rodata start is kep free for the linker to alocate it after .text. This enables users to inject sections between .text and .rodata and removes the chance to get overlapping address errors. With this the linker will by default place .rodata after .text as before. This commit also adds and exposes a few more stable address start/end symbols (__[se]uninit, __stext, __srodata) that are usefull for debugging and hooking into. See https://github.com/rust-embedded/cortex-m-rt/pull/287#issuecomment-810017930 for discussion of the issues and description of this compromise solution.
2021-04-02Minor documentation fix.Gravatar Jakub Duchniewicz 1-0/+1
2021-03-02Fix examples build for nightlyGravatar Adam Greig 1-0/+1
2021-03-02Merge #315Gravatar bors[bot] 1-1/+1
315: Use volatile read for ICSR register r=adamgreig a=lulf This prevents the compiler from optimizing the read. Edit: I also added a change to include the 9th bit in the IRQ. I can leave that out if it would break anything. #314 Co-authored-by: Ulf Lilleengen <ulf.lilleengen@gmail.com>
2021-03-02Allow nightly CI to failGravatar Adam Greig 1-0/+1
2021-02-25Read all bits from ICSR registerGravatar Ulf Lilleengen 1-1/+1
The 9th bit is needed to all 480 interrupts on Cortex-M33
2021-02-25Use volatile read for ICSR registerGravatar Ulf Lilleengen 1-1/+1
This prevents the compiler from optimizing the read
2021-01-27Update changelogGravatar Jonas Schievink 1-0/+16
2021-01-27Only emit link_section for cortex-m.Gravatar Adam Greig 2-10/+8
Previously we always emitted link_section, even though it only had an effect when our linker script was being used (and only made sense on cortex-m targets). This breaks building the code for a MacOS target, which is occasionally useful for running `cargo check` etc. In the macros crate we don't have the target information available, so instead we continue to emit link_section except specifically on MacOS.
2021-01-27Forward-port v0.6.12/13 changelogGravatar Jonas Schievink 1-1/+16
2021-01-26Add compile-fail testGravatar Jonas Schievink 1-0/+16
2021-01-26Check presence of exceptionsGravatar Jonas Schievink 1-5/+21
2021-01-26add host build test; rename "crate" to "examples" in others to clarifyGravatar Anatol Ulrich 1-7/+9
2021-01-26fix .HardFault.user section name for macosGravatar Anatol Ulrich 1-1/+2
2021-01-26Merge branch 'master' of ssh://github.com/rust-embedded/cortex-m-rtGravatar Anatol Ulrich 1-1/+1
2021-01-26Update cortex-m to 0.7.1Gravatar Jonas Schievink 1-1/+1
2021-01-25fix #74Gravatar Anatol Ulrich 1-4/+8
2021-01-21Merge #301Gravatar bors[bot] 14-163/+133
301: Initialize RAM in assembly r=adamgreig a=jonas-schievink Fixes #300 Co-authored-by: Jonas Schievink <jonasschievink@gmail.com> Co-authored-by: Adam Greig <adam@adamgreig.com>
2021-01-21Update Reset-in-asm.Gravatar Adam Greig 13-173/+134
* Use arm-none-eabi-gcc to assemble, allowing use of preprocessor to conditionally enable the FPU for eabihf targets. * Remove has_fpu configuration from build.rs. * Remove FpuTrampoline as no longer required. * Remove the Rust Reset method entirely, since the asm Reset can now enable FPU and jump to user main.
2021-01-08Allow using the crate with custom target JSON specsGravatar Jonas Schievink 1-3/+14
2021-01-08Fix compile-fail test error messageGravatar Jonas Schievink 1-1/+1
2021-01-06Update `PreResetTrampoline` docsGravatar Jonas Schievink 1-2/+2
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