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2023-10-16Move cortex-m crate into cortex-m directoryGravatar Adam Greig 17-4043/+0
2023-02-27nvic: do not require `&mut self` for `request`.Gravatar Dario Nieuwenhuis 1-4/+3
2022-11-12Merge #422Gravatar bors[bot] 1-2/+10
422: Add ITNS field to NVIC peripheral r=adamgreig a=sphw This PR adds the ITNS (Interrupt Target Non-secure) field to the NIVC peripheral. This field is required to write a boot loader for TrustZone-M devices, since it allows the user to use interrupts from non-secure states. I believe I have maintained the correct padding for the next fields, but I have not tested these changes on a non M33 device. So a close review and test would be appreciated. Co-authored-by: Sascha Wise <me@saschawise.com>
2022-08-11Add implementation for critical-section 1.0Gravatar Dario Nieuwenhuis 2-5/+3
Co-Authored-By: Markus Reiter <me@reitermark.us>
2022-07-16fix and cleanup offsets in nvicGravatar Sascha Wise 1-6/+7
2022-03-27Add on-target testsGravatar Alex Martens 1-0/+12
2022-02-25Fix cortex-m-rt qemu test by removing 'nomem' from semihosting_syscall asm, ↵Gravatar Adam Greig 1-1/+1
add inline to most cortex_m::asm methods
2022-02-24Tweaks to enable building and doctesting on host platformGravatar Adam Greig 1-3/+0
2022-02-24Add a free() method for non-cortex-m build targets that panics, to allow ↵Gravatar Adam Greig 1-1/+0
checking code that uses it on native platform.
2022-02-24Remove outlined asm, replace with stable inline asm.Gravatar Adam Greig 1-0/+2
2022-02-15add itns field to NVIC perphGravatar Sascha Wise 1-1/+8
2022-01-12Update GHA for integrated cortex-m-rtGravatar Adam Greig 1-0/+1
2022-01-06remove the ptr() function in favor of the PTR constantGravatar Tyler Holmes 9-142/+52
Per #370/#235, the const fn ptr() was supposed to be deprecated and subsequently removed. This PR removes it for the master branch tracking the 0.8 release
2022-01-06TPIU: improve SWOSupports documentationGravatar Viktor Sonesten 1-1/+2
2022-01-05tpiu: make SWOSupports fields publicGravatar Viktor Sonesten 1-4/+4
2021-12-31clippy cleanupGravatar Tyler Holmes 1-1/+1
2021-12-31`SCB.ICSR.VECTACTIVE` is 9 bits, not 8Gravatar Tyler Holmes 1-7/+8
Closes #332
2021-12-31Merge #366Gravatar bors[bot] 2-2/+24
366: itm: derive serde for `LocalTimestampOptions`, impl gated `TryFrom<u8>` r=adamgreig a=tmplt This PR is an upstream push of more std-features required by `cargo-rtic-scope`. If required, the `TryFrom<u8>` impl can be kept downstream. Co-authored-by: Viktor Sonesten <v@tmplt.dev>
2021-12-29Merge #367Gravatar bors[bot] 2-23/+111
367: add methods needed for cycle count comparisons r=adamgreig a=TDHolmes Extends the existing DWT comparator code to include cycle count comparisons which fire a `DebugMonitor` exception, if enabled with `enable_debug_monitor`. See working example [here](https://github.com/TDHolmes/embedded-profiling/blob/58d8b106921977816e2b5a05bcb43e976197edaf/ep-dwt/src/lib.rs#L57) Co-authored-by: Tyler Holmes <tyler@holmesengineering.com>
2021-12-19Switch "native" check from being x86_64 only to checking `HOST`Gravatar Tyler Holmes 3-12/+12
If `HOST==TARGET`, we know we're compiling natively. Set a new `rustc` cfg for this and use it where we previously checked for `x86_64`.
2021-12-19make intra-doc linkGravatar Tyler Holmes 1-1/+1
2021-12-19remove unused errorGravatar Tyler Holmes 1-2/+0
2021-12-19change has_cycle_counter to a recommended end user callGravatar Tyler Holmes 1-7/+4
2021-12-19fix fields, SBZ as needed for address compareGravatar Tyler Holmes 1-3/+7
2021-12-19enable has_cycle_counter for all arches. armv6m always returns falseGravatar Tyler Holmes 1-2/+5
2021-12-19SBZ fields as needed, check if block supports cycle count compareGravatar Tyler Holmes 1-4/+21
2021-12-19tidy up doc commentsGravatar Tyler Holmes 1-5/+4
2021-12-19further comments - factor out function selection and more documentationGravatar Tyler Holmes 1-8/+30
2021-12-19review suggestionsGravatar Tyler Holmes 1-41/+36
2021-12-19more correct commentGravatar Tyler Holmes 1-1/+1
2021-12-19inlineGravatar Tyler Holmes 1-0/+2
2021-12-19add methods needed for cycle count comparisonsGravatar Tyler Holmes 2-15/+66
2021-12-07feature gates: std-map -> stdGravatar Viktor Sonesten 2-3/+3
The alternative is to create another std-* gate for each std-related functionality. I do not think this will scale well, and makes the crate difficult to use. If the end-user wants to use host-side functionality they will only need to specify "std".
2021-12-07itm: derive serde for LocalTimestampOptions, impl gated TryFrom<u8>Gravatar Viktor Sonesten 1-0/+22
2021-11-27Merge #342Gravatar bors[bot] 5-36/+461
342: Implement various interfaces for trace configuration r=adamgreig a=tmplt I'm working on tracing support and aim to implement functions that abstract the configuration of relevant peripherals. Of chief interest is `DWT`, `ITM` and `TPIU`. Some propored abstractions will go against what is established in the crate; I will ask for comments on these. Co-authored-by: Viktor Sonesten <v@tmplt.dev>
2021-11-27dwt: refactor enable_exception_tracing into enable/disable funsGravatar Viktor Sonesten 1-3/+15
2021-11-21dwt, itm, tpiu: derive common traits for structs/enumsGravatar Viktor Sonesten 3-10/+11
As per Rust API guidelines: <https://rust-lang.github.io/api-guidelines/interoperability.html#c-common-traits>.
2021-11-21tpiu: improve TYPE field documentationGravatar Viktor Sonesten 1-1/+1
2021-11-21tpiu: use bitfield for SPPRGravatar Viktor Sonesten 1-2/+41
2021-11-21itm: properly document ITMSettingsGravatar Viktor Sonesten 1-1/+1
2021-11-21dwt: mark ComparatorFunction, DwtError as non-exhaustiveGravatar Viktor Sonesten 1-0/+2
A DWT unit can do much more than just comparing addresses. PC comparison, for example, which is only possible with the first DWT unit.
2021-11-21dwt: DWTError -> DwtError for in-crate consistencyGravatar Viktor Sonesten 1-2/+2
2021-11-21tpiu: remove get_ prefix, as per Rust API guidelinesGravatar Viktor Sonesten 1-1/+1
2021-11-21dwt: refactor out unnecessary explicit panicGravatar Viktor Sonesten 1-28/+24
2021-11-21dwt: don't inline Comparator::configureGravatar Viktor Sonesten 1-2/+2
The function is a bit too large to warrant inlining.
2021-11-21dwt: improve EmitOption docstringGravatar Viktor Sonesten 1-1/+2
2021-11-21dwt: fix clippy::bool_comparisonGravatar Viktor Sonesten 1-4/+4
2021-11-21dwt, itm, tpiu: remove get_ prefix, as per Rust API guidelinesGravatar Viktor Sonesten 3-28/+28
2021-11-20scb: derive serde, Hash, PartialOrd for VectActive behind gatesGravatar Viktor Sonesten 1-0/+6
Exposes two new feature gates for VectActive serde::{Serialize, Deserialize} (via "serde") and Hash, PartialOrd (via "std-map") for use on host-side ITM tracing programs. While the struct itself is not received directly over ITM, its use greatly simplifies the implementation by allowing VectActive as keys in map collections and file/socket {,de}serialization to forward the structure elsewhere. These features are not enabled by default. Before this patch, serde functionality could be realized via [0], but this does not propagate down a dependency chain (i.e. if realized for crate B, which crate A depends on, serde functionality is not exposed in crate A unless VectActive is wrapped in a type from crate B). I am not aware of any method to realize PartialOrd, Hash derivation for a downstream crate. [0] https://serde.rs/remote-derive.html
2021-10-27Merge branch 'master' into feat/tracingGravatar Viktor Sonesten 5-6/+294
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