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path: root/macros/src/codegen/assertions.rs (follow)
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2023-03-01Add rtic-timer (timerqueue + monotonic) and rtic-monotonics (systick-monotonic)Gravatar Emil Fresk 1-53/+0
2023-03-01Min codegenGravatar Emil Fresk 1-5/+0
2023-03-01RTIC v2: Initial commitGravatar Emil Fresk 1-6/+4
rtic-syntax is now part of RTIC repository
2023-01-22Handle more cfgs, support cfg on HW/SW tasksGravatar Henrik Tjäder 1-0/+2
2022-07-27Remove use of basepri register on thumbv8m.baseGravatar David Watson 1-5/+6
The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-05-24Fix clash with defmtGravatar Emil Fresk 1-1/+5
2022-03-02Added support for SRP based scheduling for armv6mGravatar Per Lindgren 1-2/+30
2020-12-10More workGravatar Emil Fresk 1-1/+7
2020-09-01Remove stale code, fix comment stylingGravatar Henrik Tjäder 1-16/+0
2020-09-01Cargo fmtGravatar Henrik Tjäder 1-6/+6
2020-09-01Brutally yank out multicoreGravatar Henrik Tjäder 1-8/+10
2020-06-11Rename RTFM to RTICGravatar Henrik Tjäder 1-3/+3
2019-06-24Monotonic trait is safe; add MultiCore traitGravatar Jorge Aparicio 1-2/+9
2019-06-13rtfm-syntax refactor + heterogeneous multi-core supportGravatar Jorge Aparicio 1-0/+26