Add logical x2APIC ID helpers and x2APIC IPI implementation.

4 files changed, 189 insertions, 30 deletions

diff --git a/src/apic/mod.rs b/src/apic/mod.rs
index 5488491..0bce5c6 100644
--- a/src/apic/mod.rs
+++ b/src/apic/mod.rs
@@ -1,5 +1,7 @@
 //! Register information and driver to program xAPIC, X2APIC and I/O APIC
 
+use bit_field::BitField;
+
 pub mod ioapic;
 pub mod x2apic;
 pub mod xapic;
@@ -81,9 +83,31 @@ pub enum DestinationShorthand {
 pub struct Icr(u64);
 
 impl Icr {
-    /// Short-hand to create a Icr value.
-    #[allow(clippy::too_many_arguments)]
-    pub fn new(
+    fn id_to_xapic_destination(destination: ApicId) -> u64 {
+        // XApic destination are encoded in bytes 56--63 in the Icr
+        match destination {
+            ApicId::XApic(d) => (d as u64) << 56,
+            ApicId::X2Apic(_d) => {
+                unreachable!("x2APIC IDs are not supported for xAPIC (use the x2APIC controller)")
+            }
+        }
+    }
+
+    fn id_to_x2apic_destination(destination: ApicId) -> u64 {
+        // whereas, X2Apic destinations are encoded in bytes 32--63 in the Icr
+        // The ACPI tables will can name the first 255 processors
+        // with xAPIC IDs and no x2APIC entry exists in SRAT
+        // However, the IDs should be compatible (I hope)
+        let d: u64 = match destination {
+            ApicId::XApic(d) => d as u64,
+            ApicId::X2Apic(d) => d as u64,
+        };
+
+        d << 32
+    }
+
+    fn new(
+        dest_encoder: fn(ApicId) -> u64,
         vector: u8,
         destination: ApicId,
         destination_shorthand: DestinationShorthand,
@@ -93,14 +117,7 @@ impl Icr {
         level: Level,
         trigger_mode: TriggerMode,
     ) -> Icr {
-        let destination: u8 = match destination {
-            ApicId::XApic(d) => d,
-            ApicId::X2Apic(_d) => {
-                unreachable!("x2APIC destinations currently unsupported, adjust Icr construction!")
-            }
-        };
-
-        Icr((destination as u64) << 56
+        Icr(dest_encoder(destination)
             | (destination_shorthand as u64) << 18
             | (trigger_mode as u64) << 15
             | (level as u64) << 14
@@ -110,6 +127,55 @@ impl Icr {
             | (vector as u64))
     }
 
+    /// Short-hand to create a Icr value that will work for an x2APIC controller.
+    #[allow(clippy::too_many_arguments)]
+    pub fn for_x2apic(
+        vector: u8,
+        destination: ApicId,
+        destination_shorthand: DestinationShorthand,
+        delivery_mode: DeliveryMode,
+        destination_mode: DestinationMode,
+        delivery_status: DeliveryStatus,
+        level: Level,
+        trigger_mode: TriggerMode,
+    ) -> Icr {
+        Icr::new(
+            Icr::id_to_x2apic_destination,
+            vector,
+            destination,
+            destination_shorthand,
+            delivery_mode,
+            destination_mode,
+            delivery_status,
+            level,
+            trigger_mode,
+        )
+    }
+
+    #[allow(clippy::too_many_arguments)]
+    pub fn for_xapic(
+        vector: u8,
+        destination: ApicId,
+        destination_shorthand: DestinationShorthand,
+        delivery_mode: DeliveryMode,
+        destination_mode: DestinationMode,
+        delivery_status: DeliveryStatus,
+        level: Level,
+        trigger_mode: TriggerMode,
+    ) -> Icr {
+        Icr::new(
+            Icr::id_to_xapic_destination,
+            vector,
+            destination,
+            destination_shorthand,
+            delivery_mode,
+            destination_mode,
+            delivery_status,
+            level,
+            trigger_mode,
+        )
+    }
+
     /// Get lower 32-bits of the Icr register.
     pub fn lower(&self) -> u32 {
         self.0 as u32
@@ -130,6 +196,43 @@ pub enum ApicId {
     X2Apic(u32),
 }
 
+impl ApicId {
+    /// Returns the Logical x2APIC ID.
+    ///
+    /// In x2APIC mode, the 32-bit logical x2APIC ID, which can be read from LDR,
+    /// is derived from the 32-bit local x2APIC ID:
+    /// Logical x2APIC ID = [(x2APIC ID[19:4] « 16) | (1 « x2APIC ID[3:0])]
+    pub fn x2apic_logical_id(&self) -> u32 {
+        self.x2apic_logical_cluster_id() << 16 | 1 << self.x2apic_logical_cluster_address()
+    }
+
+    /// Returns the logical address relative to a cluster
+    /// for a given APIC ID (assuming x2APIC addressing).
+    pub fn x2apic_logical_cluster_address(&self) -> u32 {
+        let d = match *self {
+            // We support conversion for XApic IDs too because ACPI can
+            // report <255 cores as XApic entries
+            ApicId::XApic(id) => id as u32,
+            ApicId::X2Apic(id) => id as u32,
+        };
+
+        d.get_bits(0..=3)
+    }
+
+    /// Returns the cluster ID a given APIC ID belongs to
+    /// (assuming x2APIC addressing).
+    pub fn x2apic_logical_cluster_id(&self) -> u32 {
+        let d = match *self {
+            // We support conversion for XApic IDs too because ACPI can
+            // report <255 cores as XApic entries
+            ApicId::XApic(id) => id as u32,
+            ApicId::X2Apic(id) => id as u32,
+        };
+
+        d.get_bits(4..=19)
+    }
+}
+
 impl Into<usize> for ApicId {
     fn into(self) -> usize {
         match self {
@@ -147,6 +250,9 @@ pub trait ApicControl {
     /// Return APIC ID.
     fn id(&self) -> u32;
 
+    /// Returns the logical APIC ID.
+    fn logical_id(&self) -> u32;
+
     /// Read APIC version
     fn version(&self) -> u32;
 
diff --git a/src/apic/x2apic.rs b/src/apic/x2apic.rs
index ceb8aad..fc23152 100644
--- a/src/apic/x2apic.rs
+++ b/src/apic/x2apic.rs
@@ -1,11 +1,11 @@
 //! x2APIC, the most recent APIC on x86 for large servers with more than 255 cores.
 use bit_field::BitField;
 
-use super::{ApicControl, ApicId, Icr};
+use super::*;
 use crate::msr::{
-    rdmsr, wrmsr, IA32_APIC_BASE, IA32_TSC_DEADLINE, IA32_X2APIC_APICID, IA32_X2APIC_ESR,
-    IA32_X2APIC_LVT_LINT0, IA32_X2APIC_LVT_TIMER, IA32_X2APIC_SELF_IPI, IA32_X2APIC_SIVR,
-    IA32_X2APIC_VERSION,
+    rdmsr, wrmsr, IA32_APIC_BASE, IA32_TSC_DEADLINE, IA32_X2APIC_APICID, IA32_X2APIC_EOI,
+    IA32_X2APIC_ESR, IA32_X2APIC_ICR, IA32_X2APIC_LDR, IA32_X2APIC_LVT_LINT0,
+    IA32_X2APIC_LVT_TIMER, IA32_X2APIC_SELF_IPI, IA32_X2APIC_SIVR, IA32_X2APIC_VERSION,
 };
 
 /// Represents an x2APIC driver instance.
@@ -39,8 +39,7 @@ impl X2APIC {
             let svr: u64 = 1 << 8 | 15;
             wrmsr(IA32_X2APIC_SIVR, svr);
 
-            //TODO: let mut lint0 = rdmsr(IA32_X2APIC_LVT_LINT0);
-            // TODO: Fix magic number
+            // TODO: Fix magic number?
             let lint0 = 1 << 16 | (1 << 15) | (0b111 << 8) | 0x20;
             wrmsr(IA32_X2APIC_LVT_LINT0, lint0);
 
@@ -71,11 +70,16 @@ impl ApicControl for X2APIC {
         (self.base & (1 << 8)) > 0
     }
 
-    /// Read local APIC ID.
+    /// Read local x2APIC ID.
     fn id(&self) -> u32 {
         unsafe { rdmsr(IA32_X2APIC_APICID) as u32 }
     }
 
+    /// In x2APIC mode, the 32-bit logical x2APIC ID, can be read from LDR.
+    fn logical_id(&self) -> u32 {
+        unsafe { rdmsr(IA32_X2APIC_LDR) as u32 }
+    }
+
     /// Read APIC version.
     fn version(&self) -> u32 {
         unsafe { rdmsr(IA32_X2APIC_VERSION) as u32 }
@@ -106,26 +110,72 @@ impl ApicControl for X2APIC {
 
     /// End Of Interrupt -- Acknowledge interrupt delivery.
     fn eoi(&mut self) {
-        unreachable!("NYI");
+        unsafe {
+            wrmsr(IA32_X2APIC_EOI, 0);
+        }
     }
 
     /// Send a INIT IPI to a core.
-    unsafe fn ipi_init(&mut self, _core: ApicId) {
-        unreachable!("NYI");
+    unsafe fn ipi_init(&mut self, core: ApicId) {
+        let icr = Icr::for_x2apic(
+            0,
+            core,
+            DestinationShorthand::NoShorthand,
+            DeliveryMode::Init,
+            DestinationMode::Physical,
+            DeliveryStatus::Idle,
+            Level::Assert,
+            TriggerMode::Level,
+        );
+        self.send_ipi(icr);
     }
 
     /// Deassert INIT IPI.
     unsafe fn ipi_init_deassert(&mut self) {
-        unreachable!("NYI");
+        let icr = Icr::for_x2apic(
+            0,
+            ApicId::X2Apic(0),
+            // INIT deassert is always sent to everyone, so we are supposed to specify:
+            DestinationShorthand::AllIncludingSelf,
+            DeliveryMode::Init,
+            DestinationMode::Physical,
+            DeliveryStatus::Idle,
+            Level::Deassert,
+            TriggerMode::Level,
+        );
+        self.send_ipi(icr);
     }
 
     /// Send a STARTUP IPI to a core.
-    unsafe fn ipi_startup(&mut self, _core: ApicId, _start_page: u8) {
-        unreachable!("NYI");
+    unsafe fn ipi_startup(&mut self, core: ApicId, start_page: u8) {
+        let icr = Icr::for_x2apic(
+            start_page,
+            core,
+            DestinationShorthand::NoShorthand,
+            DeliveryMode::StartUp,
+            DestinationMode::Physical,
+            DeliveryStatus::Idle,
+            Level::Assert,
+            TriggerMode::Edge,
+        );
+        self.send_ipi(icr);
     }
 
     /// Send a generic IPI.
-    unsafe fn send_ipi(&mut self, _icr: Icr) {
-        unreachable!("NYI");
+    unsafe fn send_ipi(&mut self, icr: Icr) {
+        wrmsr(IA32_X2APIC_ESR, 0);
+        wrmsr(IA32_X2APIC_ESR, 0);
+
+        wrmsr(IA32_X2APIC_ICR, icr.0);
+
+        loop {
+            let icr = rdmsr(IA32_X2APIC_ICR);
+            if (icr >> 12 & 0x1) == 0 {
+                break;
+            }
+            if rdmsr(IA32_X2APIC_ESR) > 0 {
+                break;
+            }
+        }
     }
 }
diff --git a/src/apic/xapic.rs b/src/apic/xapic.rs
index 51dc27f..ec4b849 100644
--- a/src/apic/xapic.rs
+++ b/src/apic/xapic.rs
@@ -327,6 +327,10 @@ impl ApicControl for XAPIC {
         self.read(ApicRegister::XAPIC_ID)
     }
 
+    fn logical_id(&self) -> u32 {
+        self.read(ApicRegister::XAPIC_LDR)
+    }
+
     /// Read APIC version
     fn version(&self) -> u32 {
         self.read(ApicRegister::XAPIC_VERSION)
@@ -358,7 +362,7 @@ impl ApicControl for XAPIC {
 
     /// Send a INIT IPI to a core.
     unsafe fn ipi_init(&mut self, core: ApicId) {
-        let icr = Icr::new(
+        let icr = Icr::for_xapic(
             0,
             core,
             DestinationShorthand::NoShorthand,
@@ -373,7 +377,7 @@ impl ApicControl for XAPIC {
 
     /// Deassert INIT IPI.
     unsafe fn ipi_init_deassert(&mut self) {
-        let icr = Icr::new(
+        let icr = Icr::for_xapic(
             0,
             ApicId::XApic(0),
             // INIT deassert is always sent to everyone, so we are supposed to specify:
@@ -389,7 +393,7 @@ impl ApicControl for XAPIC {
 
     /// Send a STARTUP IPI to a core.
     unsafe fn ipi_startup(&mut self, core: ApicId, start_page: u8) {
-        let icr = Icr::new(
+        let icr = Icr::for_xapic(
             start_page,
             core,
             DestinationShorthand::NoShorthand,
diff --git a/src/bits64/syscall.rs b/src/bits64/syscall.rs
index a4ad0f5..4753b36 100644
--- a/src/bits64/syscall.rs
+++ b/src/bits64/syscall.rs
@@ -14,7 +14,6 @@
 //! * Only values of class INTEGER or class MEMORY are passed to the kernel.
 //!
 //! This code is inspired by the syscall.rs (https://github.com/kmcallister/syscall.rs/) project.
-//!
 #[macro_export]
 macro_rules! syscall {
     ($arg0:expr) => {