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| author |  Gerd Zellweger <mail@gerdzellweger.com>
| 2020-11-07 13:05:35 -0800 |
|---|---|---|
| committer | Gerd Zellweger <mail@gerdzellweger.com>
| 2020-11-07 13:05:35 -0800 |
| commit | b5e83dabc384fcaa9e59d8faf29a587ca732362d (patch) | |
| tree | 406325dd0ab6dcb55ebf93f868976cc2523e965c | |
| parent | abbdb0a45203fbdc1f5b6b126fd0784d310ef60f (diff) | |
| download | rust-x86-b5e83dabc384fcaa9e59d8faf29a587ca732362d.tar.gz rust-x86-b5e83dabc384fcaa9e59d8faf29a587ca732362d.tar.zst rust-x86-b5e83dabc384fcaa9e59d8faf29a587ca732362d.zip | |
Enable deadline mode in x2apic properly.
| -rw-r--r-- | src/apic/x2apic.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/apic/x2apic.rs b/src/apic/x2apic.rs index fc23152..696b69b 100644 --- a/src/apic/x2apic.rs +++ b/src/apic/x2apic.rs @@ -89,14 +89,14 @@ impl ApicControl for X2APIC { fn tsc_enable(&mut self, vector: u8) { unsafe { let mut lvt: u64 = rdmsr(IA32_X2APIC_LVT_TIMER); - // Set vector lvt &= !0xff; lvt |= vector as u64; + // Unmask timer IRQ lvt.set_bit(16, false); // Enable TSC deadline mode lvt.set_bit(17, false); - lvt.set_bit(18, false); + lvt.set_bit(18, true); wrmsr(IA32_X2APIC_LVT_TIMER, lvt); } } |