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authorGravatar Brian Martin <bmartin@twitter.com> 2019-02-14 14:32:21 -0800
committerGravatar Brian Martin <bmartin@twitter.com> 2019-02-14 14:52:15 -0800
commit8f30a2fc3d5d73f90a4ba64d0a90348e59e7967b (patch)
treeb9d29e6e317c5f3b23c8a88127c42d72b750cff4 /src/controlregs.rs
parent4c838b6691b6ec47a08b5be327b90bd2423203e2 (diff)
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update to Rust 2018 edition
* specify 2018 edition in the manifest * changes to fix build with 2018 edition
Diffstat (limited to 'src/controlregs.rs')
-rw-r--r--src/controlregs.rs4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/controlregs.rs b/src/controlregs.rs
index 1445eab..02855bb 100644
--- a/src/controlregs.rs
+++ b/src/controlregs.rs
@@ -1,7 +1,9 @@
//! Functions to read and write control registers.
//! See Intel Vol. 3a Section 2.5, especially Figure 2-7.
-use arch::{_xgetbv, _xsetbv};
+use bitflags::*;
+
+use crate::arch::{_xgetbv, _xsetbv};
bitflags! {
pub struct Cr0: usize {