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| author |  bors[bot] <26634292+bors[bot]@users.noreply.github.com>
| 2019-07-29 20:22:11 +0000 |
|---|---|---|
| committer | bors[bot] <26634292+bors[bot]@users.noreply.github.com>
| 2019-07-29 20:22:11 +0000 |
| commit | 1aa7d5dba9f3a50d1568bcfddc4073ac08d4ee1e (patch) | |
| tree | 09e8c83bc0e843c20e5f1589f702e945d335d4a8 /src/peripheral/cpuid.rs | |
| parent | 6a213910f7f8920906c2f8882cbc1f1a3ebc3627 (diff) | |
| parent | 9987c6f9e77d50feb6b77be4c9eae84a988e1fdf (diff) | |
| download | cortex-m-1aa7d5dba9f3a50d1568bcfddc4073ac08d4ee1e.tar.gz cortex-m-1aa7d5dba9f3a50d1568bcfddc4073ac08d4ee1e.tar.zst cortex-m-1aa7d5dba9f3a50d1568bcfddc4073ac08d4ee1e.zip | |
Merge #160
160: Update for 2018 edition r=korken89 a=adamgreig
Co-authored-by: Adam Greig <adam@adamgreig.com>
Diffstat (limited to 'src/peripheral/cpuid.rs')
| -rw-r--r-- | src/peripheral/cpuid.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/peripheral/cpuid.rs b/src/peripheral/cpuid.rs index c79ad18..7b86ddc 100644 --- a/src/peripheral/cpuid.rs +++ b/src/peripheral/cpuid.rs @@ -5,7 +5,7 @@ use volatile_register::RO; use volatile_register::RW; #[cfg(not(armv6m))] -use peripheral::CPUID; +use crate::peripheral::CPUID; /// Register block #[repr(C)] @@ -104,7 +104,7 @@ impl CPUID { const CCSIDR_ASSOCIATIVITY_MASK: u32 = 0x3FF << CCSIDR_ASSOCIATIVITY_POS; self.select_cache(level, ind); - ::asm::dsb(); + crate::asm::dsb(); let ccsidr = self.ccsidr.read(); ( (1 + ((ccsidr & CCSIDR_NUMSETS_MASK) >> CCSIDR_NUMSETS_POS)) as u16, |