aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2023-10-16Move cortex-m crate into cortex-m directoryGravatar Adam Greig 55-307/+113
2023-10-13Merge pull request #486 from newAM/update-actions-checkoutGravatar Adam Greig 6-11/+11
actions/checkout: 3 -> 4
2023-10-13actions/checkout: 3 -> 4Gravatar Alex Martens 6-11/+11
This is the same thing but updated from nodejs 16 to 20.
2023-08-16Merge pull request #476 from diondokter/optional-hardfault-trampolineGravatar Adam Greig 8-87/+275
Hardfault trampoline is now optional
2023-08-16Add to docsGravatar Dion Dokter 1-9/+23
2023-07-21Add readme with test running clarificationGravatar Dion Dokter 1-0/+7
2023-07-21fmtGravatar Dion Dokter 1-2/+1
2023-07-21Changed setup for better compiler diagnostics. We won't get a nasty assembly ↵Gravatar Dion Dokter 3-7/+39
error anymore
2023-07-21Changed some names around so everything should be called correctlyGravatar Dion Dokter 1-18/+14
2023-07-12Merge pull request #482 from hannobraun/patch-1Gravatar Alex Martens 1-1/+1
Fix word in comment
2023-07-12Merge pull request #483 from rust-embedded/ghmqGravatar Adam Greig 6-20/+15
Swap to GHMQ
2023-07-11Swap to GHMQGravatar Adam Greig 6-20/+15
2023-07-07Fix word in commentGravatar Hanno Braun 1-1/+1
2023-06-20Added more tests and fixed a panicGravatar Dion Dokter 3-18/+62
2023-06-16Removed the feature flag and moved the trampoline into the macroGravatar Dion Dokter 5-120/+159
2023-05-19typoGravatar Dion Dokter 1-1/+1
2023-05-19Update changelogGravatar Dion Dokter 1-0/+3
2023-05-19Fix clippy warningsGravatar Dion Dokter 1-2/+2
2023-05-19Hardfault trampoline is now optionalGravatar Dion Dokter 4-2/+56
2023-03-21Merge #474Gravatar bors[bot] 2-7/+6
474: Upgrade syn to version 2.0 r=adamgreig a=jannic Co-authored-by: Jan Niehusmann <jan@gondor.com>
2023-03-18Upgrade syn to version 2.0Gravatar Jan Niehusmann 2-7/+6
2023-02-26Merge #472Gravatar bors[bot] 2-4/+7
472: nvic: do not require `&mut self` for `request`. r=adamgreig a=Dirbaio It's not needed, the register write is stateless/atomic. Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-02-27nvic: do not require `&mut self` for `request`.Gravatar Dario Nieuwenhuis 2-4/+7
2023-02-17Merge #455Gravatar bors[bot] 5-8/+37
455: Add zero-init-ram feature r=adamgreig a=inorick Add the 'zero-init-ram' feature that initializes the RAM with zeros during startup. This is normally not necessary but might be required on custom hardware. If this step is skipped on such hardware, reading from memory that was never written to will cause a hard-fault. Co-authored-by: Norbert Fabritius <norbert.fabritius@esrlabs.com> Co-authored-by: Adam Greig <adam@adamgreig.com>
2023-02-17Move zero-init-ram to just before bss initialisation, so that pre_init ↵Gravatar Adam Greig 2-15/+18
occurs before
2023-02-17Skip .bss memory init if zero-init-ram is activeGravatar Norbert Fabritius 1-0/+1
2023-02-17zero-init-ram: Expand comment above asm codeGravatar Norbert Fabritius 1-2/+2
2023-02-17Add documentation, test and changelog entry for `zero-init-ram` featureGravatar Norbert Fabritius 3-2/+11
2023-02-17Fix _ram_start and _ram_end orderGravatar Norbert Fabritius 2-5/+5
2023-02-17Add zero-init-ram featureGravatar Norbert Fabritius 3-9/+25
Add the 'zero-init-ram' feature that initializes the RAM with zeros during startup. This is normally not necessary but might be required on custom hardware. If this step is skipped on such hardware, reading from memory that was never written to will cause a hard-fault.
2023-02-14Merge #470c-m-rt-v0.7.3Gravatar bors[bot] 2-4/+15
470: Prepare for cortex-m-rt v0.7.3 r=thalesfragoso a=adamgreig This fixes the miscompilation in #467, so I'd like to release it as soon as possible. Co-authored-by: Adam Greig <adam@adamgreig.com>
2023-02-14Prepare for cortex-m-rt v0.7.3Gravatar Adam Greig 2-4/+15
2023-02-14Merge #467Gravatar bors[bot] 1-15/+1
467: cortex-m-rt: Remove LR push, to ensure the stack is 8-byte aligned. r=adamgreig a=Dirbaio This was causing incorrect execution of code optimized with the assumption the stack is 8-byte aligned. Alternate version of #463 - Remove instead of fix the sentinel/fake frame. - Remove code initializing LR, since it's now clobbered by the `bl main` anyway. - ~~Remove the .cfi directives, since Reset now has no correct CFI info. I think this is the "correct" thing to do here.~~ - ~~Initialize the frame pointer in R7 (suggestion from `@jamesmunns)~~` Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-02-14cortex-m-rt: Remove LR push, to ensure the stack is 8-byte aligned.Gravatar Dario Nieuwenhuis 1-15/+1
This was causing incorrect execution of code optimized with the assumption the stack is 8-byte aligned.
2023-02-12Merge #465Gravatar bors[bot] 3-4/+17
465: Enforce 8-byte initial stack pointer alignment r=adamgreig a=adamgreig After #463 we discovered that adding a second linker script via another compiler flag could be used to override `_stack_start` without triggering the assert in the main linker script. By masking the value, we force alignment even when the assert doesn't otherwise trigger. Co-authored-by: Adam Greig <adam@adamgreig.com>
2023-02-11Enforce 8-byte initial stack pointer alignmentGravatar Adam Greig 3-4/+17
2023-02-11Merge #464Gravatar bors[bot] 1-0/+6
464: cortex-m-rt: assert in linker script that stack_start is 8-byte aligned. r=adamgreig a=Dirbaio If the user sets RAM length to something that's not multiple of 8, the stack won't be 8-byte aligned. This'll trigger the same horrible symptoms as #463 . This PR adds an assert to the linker script that enforces alignment. Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-02-11cortex-m-rt: assert in linker script that stack_start is 8-byte aligned.Gravatar Dario Nieuwenhuis 1-0/+6
2023-01-28Merge #462Gravatar bors[bot] 1-1/+1
462: panic-itm: update crate config so docs aren't empty r=newAM a=tgross35 The docs are currently empty since the module is disabled https://docs.rs/panic-itm/0.4.2/panic_itm/index.html Co-authored-by: Trevor Gross <tmgross@umich.edu>
2023-01-25panic-itm: update crate config so docs aren't emptyGravatar Trevor Gross 1-1/+1
2022-11-12Merge #422Gravatar bors[bot] 1-2/+10
422: Add ITNS field to NVIC peripheral r=adamgreig a=sphw This PR adds the ITNS (Interrupt Target Non-secure) field to the NIVC peripheral. This field is required to write a boot loader for TrustZone-M devices, since it allows the user to use interrupts from non-secure states. I believe I have maintained the correct padding for the next fields, but I have not tested these changes on a non M33 device. So a close review and test would be appreciated. Co-authored-by: Sascha Wise <me@saschawise.com>
2022-11-08Merge #454c-m-rt-v0.7.2Gravatar bors[bot] 3-3/+13
454: Prepare for cortex-m-rt 0.7.2 r=therealprof a=adamgreig It's been about a year since the last release so may as well get the couple of bug fixes and new assembly out, I think. This also adds the new set-vtor and set-sp features. Co-authored-by: Adam Greig <adam@adamgreig.com>
2022-11-08Prepare for c-m-rt 0.7.2Gravatar Adam Greig 3-3/+13
2022-09-04Merge #451Gravatar bors[bot] 3-26/+40
451: Small critical-section-related fixes. r=adamgreig a=Dirbaio See individual commit messages. Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-08-22Document critical-section-single-core feature.Gravatar Dario Nieuwenhuis 1-0/+10
2022-08-22Use a `mod _export` for macro reexports.Gravatar Dario Nieuwenhuis 3-25/+26
This avoids having to do `#[doc(hidden)] pub mod critical_section` which is a bit strange.
2022-08-22Fix outdated comment in `singleton!`.Gravatar Dario Nieuwenhuis 1-1/+4
2022-08-12Merge #447Gravatar bors[bot] 18-52/+95
447: Add implementation for critical-section 1.0 r=adamgreig a=Dirbaio Picking up #433 since it seems stalled. Changes from #433 are: - Update to `critical-section 1.0.0-alpha.2` - Use `bool` restore token - Name Cargo feature `critical-section-single-core`. TODO before merging: - [x] Wait for `critical-section 1.0` release https://github.com/rust-embedded/critical-section/pull/19 Co-Authored-By: Markus Reiter `@reitermarkus` Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-08-12Merge #450Gravatar bors[bot] 1-2/+2
450: Fix CI compiletest breakage due to Rust 1.63 r=adamgreig a=Dirbaio Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-08-12Fix CI compiletest breakage due to Rust 1.63Gravatar Dario Nieuwenhuis 1-2/+2
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-31 01:27:49 +0000