Age | Commit message (Collapse) | Author | Files | Lines | |
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2019-10-29 | Add another missing #[inline]. | 1 | -0/+1 | ||
2019-10-29 | Add `#[inline]` to some more functions. | 5 | -0/+27 | ||
Now the only public non-inline functions left are: - write_all - write_aligned - All (derived) Debug implementations (Checked using Clippy's missing_inline_in_public_items lint.) | |||||
2019-10-29 | Add `#[inline]` to lots of trivial functions. | 8 | -0/+75 | ||
2019-10-28 | Merge #172 | 11 | -49/+53 | ||
172: Make Clippy happy. r=therealprof a=m-ou-se Co-authored-by: Mara Bos <m-ou.se@m-ou.se> | |||||
2019-10-15 | add a safe method to software unlock the DWT | 1 | -0/+9 | ||
today the alternative is an unsafe write to the LAR register | |||||
2019-10-09 | Make Clippy happy. | 11 | -49/+53 | ||
2019-09-21 | Deprecate nonexistent registers on thumbv8m.base | 1 | -3/+24 | ||
First step in resolving #155 | |||||
2019-09-10 | Make some trivial functions eligible for inlining | 1 | -0/+14 | ||
2019-09-08 | Remove unnecessary unsafe block | 1 | -1/+1 | ||
2019-09-08 | Fix errors and warnings | 1 | -16/+14 | ||
2019-09-06 | Allow writing to the CONTROL register | 1 | -2/+63 | ||
2019-08-11 | Add {M,P}SPLIM access routines found on ARMv8-M | 3 | -0/+100 | ||
Signed-off-by: Aurabindo Jayamohanan <mail@aurabindo.in> | |||||
2019-07-29 | Fix missing `crate::` | 2 | -2/+2 | ||
2019-07-29 | Update for 2018 edition | 13 | -70/+59 | ||
2019-07-24 | Define MSRV to be 1.31.0 and unconditionally use const-fn | 1 | -4/+3 | ||
2019-06-19 | add NVIC::{mask,unmask} | 1 | -5/+26 | ||
these are the "static method" (methods that don't take `self`) versions of NVIC::{enable,disable} in the same vein as the existing NVIC::{pend,unpend} this commit also deprecates the existing NVIC::{enable,disable} methods and notes that NVIC::enable is unsound because it should be an `unsafe` method (like interrupt::enable and basepri::write, it can break critical sections) but it's marked as safe. Its replacement, NVIC::unmask, has the correct unsafety setting: it's an `unsafe` function. | |||||
2019-06-13 | Remove debug_assert from Peripherals::steal | 1 | -2/+0 | ||
2019-04-24 | Derive Debug, PartialEq and Eq for more types | 3 | -2/+3 | ||
2019-04-14 | Merge #138 | 1 | -0/+20 | ||
138: scb: add static version of system_reset as sys_reset r=korken89 a=hdhoang As suggested in https://github.com/ah-/anne-key/pull/94. I branched this off v0.5.8 to verify the function in that PR, and against rtfm v0.3 in https://github.com/hdhoang/anne-key/commit/d6fb831cbbb46bc10a6184b78bf13e00245234d6 I have cloned the body of `system_reset`, do you think we should call one from the other (e.g. ignoring `self` in `system_reset`, or stealing `Peripherals` in `system_reset2`)? Co-authored-by: Hoàng Đức Hiếu <code@hdhoang.space> | |||||
2019-04-13 | deprecate system_reset in favor of static sys_reset | 1 | -3/+2 | ||
2019-03-21 | scb: add static version of system_reset as system_reset2 | 1 | -0/+21 | ||
2019-03-12 | Merge #106 | 3 | -6/+54 | ||
106: Stir register and debugger check r=adamgreig a=thenewwazoo Adds support for requesting an interrupt via the STIR register and checking whether a debugger is attached. Co-authored-by: Brandon Matthews <bmatthews@zipcar.com> Co-authored-by: Brandon Matthews <bmatthews@optimaltour.us> | |||||
2019-03-12 | Merge #127 | 2 | -1/+29 | ||
127: Cortex M0(+) DWT fixes r=adamgreig a=korken89 The current DWT setup has a lot of registers that are not available in Cortex-M0(+), fixes are added here. Co-authored-by: Emil Fresk <emil.fresk@gmail.com> | |||||
2019-03-12 | Fix STIR register test, remove armv6m-related offsets in NVIC | 1 | -5/+2 | ||
2019-03-12 | Merge #97 | 2 | -2/+2 | ||
97: Rename `shcrs` to `shcsr` in `scb::RegisterBlock` r=adamgreig a=rajivr Commit `c290aa4e` introduced `shcrs` field to `scb::RegisterBlock`. In CMSIS, this field is `shcsr`. https://github.com/ARM-software/CMSIS_5/blob/5.3.0/CMSIS/Core/Include/core_cm4.h#L449 This patch changes `shcrs` to `shcsr`. Signed-off-by: Rajiv Ranganath <rajiv.ranganath@gmail.com> Co-authored-by: Rajiv Ranganath <rajiv.ranganath@gmail.com> | |||||
2019-03-12 | Update is_debugger_attached so as not to clear S_RESET_ST and S_RETIRE_ST | 1 | -8/+14 | ||
2019-03-12 | Fix rebase syntax error; disable STIR test on armv6m | 2 | -0/+2 | ||
2019-03-12 | Expand is_debugger_attached note | 1 | -2/+5 | ||
2019-03-12 | Add explanatory note about C_DEBUGEN | 1 | -3/+9 | ||
2019-03-12 | Add note that NVIC::request is not available on armv6m | 1 | -0/+2 | ||
2019-03-12 | Exclude unused import and elide nvic::request for armv6m | 1 | -2/+3 | ||
2019-03-12 | Add STIR register address test | 1 | -0/+1 | ||
2019-03-12 | Add support for debugger check | 1 | -2/+6 | ||
2019-03-12 | Add STIR register to NVIC peripheral | 1 | -1/+27 | ||
2018-12-15 | Fix for error in Travis | 1 | -1/+3 | ||
2018-12-15 | Test fixes | 1 | -0/+8 | ||
2018-12-15 | Fixes for DWT on Cortex-M0 | 1 | -0/+18 | ||
2018-12-09 | Upgrade to aligned 0.3 | 1 | -3/+3 | ||
2018-11-20 | Add api to set SLEEPONEXIT bit in SCR register | 1 | -0/+18 | ||
2018-10-27 | deprecate NVIC.{clear,set}_pending in favor of NVIC::{un,}pend | 1 | -5/+25 | ||
NVIC::{un,}pend are static methods that don't require an instance of NVIC to be invoked. | |||||
2018-10-26 | deny warnings only on nightly | 1 | -1/+0 | ||
lints have changed between nightly and stable | |||||
2018-10-26 | remove hidden variant | 1 | -5/+0 | ||
it was there to maybe support adding DebugMonitor in the future but it has already been added | |||||
2018-10-26 | add DebugMonitor variant to SystemHandler | 1 | -2/+6 | ||
2018-10-26 | fix shift | 1 | -2/+2 | ||
2018-10-24 | fix warning | 1 | -1/+0 | ||
2018-10-24 | add high level API to set priority of system handlers | 2 | -0/+118 | ||
2018-10-01 | Autoformat scb.rs by rustfmt | 1 | -13/+14 | ||
2018-10-01 | Remove blank line | 1 | -1/+0 | ||
2018-10-01 | Fix function names and remove exclusive access | 1 | -3/+3 | ||
2018-09-24 | Fix duplicate PendSV. | 1 | -56/+28 | ||