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2021-11-25Merge #362Gravatar bors[bot] 1-0/+3
362: add note r=jonathanpallant a=gnxlxnxx the same note as in https://github.com/rust-embedded/riscv/pull/87 Co-authored-by: gnxlxnxx <roman@kretschmer.email>
2021-11-21dwt, itm, tpiu: derive common traits for structs/enumsGravatar Viktor Sonesten 3-10/+11
As per Rust API guidelines: <https://rust-lang.github.io/api-guidelines/interoperability.html#c-common-traits>.
2021-11-21tpiu: improve TYPE field documentationGravatar Viktor Sonesten 1-1/+1
2021-11-21tpiu: use bitfield for SPPRGravatar Viktor Sonesten 1-2/+41
2021-11-21itm: properly document ITMSettingsGravatar Viktor Sonesten 1-1/+1
2021-11-21dwt: mark ComparatorFunction, DwtError as non-exhaustiveGravatar Viktor Sonesten 1-0/+2
A DWT unit can do much more than just comparing addresses. PC comparison, for example, which is only possible with the first DWT unit.
2021-11-21dwt: DWTError -> DwtError for in-crate consistencyGravatar Viktor Sonesten 1-2/+2
2021-11-21tpiu: remove get_ prefix, as per Rust API guidelinesGravatar Viktor Sonesten 1-1/+1
2021-11-21dwt: refactor out unnecessary explicit panicGravatar Viktor Sonesten 1-28/+24
2021-11-21dwt: don't inline Comparator::configureGravatar Viktor Sonesten 1-2/+2
The function is a bit too large to warrant inlining.
2021-11-21dwt: improve EmitOption docstringGravatar Viktor Sonesten 1-1/+2
2021-11-21dwt: fix clippy::bool_comparisonGravatar Viktor Sonesten 1-4/+4
2021-11-21dwt, itm, tpiu: remove get_ prefix, as per Rust API guidelinesGravatar Viktor Sonesten 3-28/+28
2021-11-20scb: derive serde, Hash, PartialOrd for VectActive behind gatesGravatar Viktor Sonesten 1-0/+6
Exposes two new feature gates for VectActive serde::{Serialize, Deserialize} (via "serde") and Hash, PartialOrd (via "std-map") for use on host-side ITM tracing programs. While the struct itself is not received directly over ITM, its use greatly simplifies the implementation by allowing VectActive as keys in map collections and file/socket {,de}serialization to forward the structure elsewhere. These features are not enabled by default. Before this patch, serde functionality could be realized via [0], but this does not propagate down a dependency chain (i.e. if realized for crate B, which crate A depends on, serde functionality is not exposed in crate A unless VectActive is wrapped in a type from crate B). I am not aware of any method to realize PartialOrd, Hash derivation for a downstream crate. [0] https://serde.rs/remote-derive.html
2021-11-12add noteGravatar gnxlxnxx 1-0/+3
the same note as in https://github.com/rust-embedded/riscv/pull/87
2021-10-27Merge branch 'master' into feat/tracingGravatar Viktor Sonesten 6-18/+314
2021-09-24allow clippy::upper_case_acronymsGravatar Viktor Sonesten 1-0/+14
2021-09-24itm: remove useless conversionGravatar Viktor Sonesten 1-1/+1
2021-09-24itm: fix field spellingGravatar Viktor Sonesten 1-2/+2
2021-09-24dwt: feature gate trace and PC samples out of armv6mGravatar Viktor Sonesten 1-4/+4
2021-09-23Merge #348Gravatar bors[bot] 1-1/+3
348: Fix slightly misleading examples. r=adamgreig a=newAM This is a bit of a nitpick; the examples provided for the peripherals use the cycle counter as an example, but it is not properly enabled, which is slightly misleading. The examples only do `peripherals.DWT.enable_cycle_counter`, but this write may be ignored because tracing needs to be enabled first. Co-authored-by: Alex Martens <alexmgit@protonmail.com>
2021-09-23Merge #352Gravatar bors[bot] 2-0/+124
352: Add the Cortex-M7 TCM and cache access control registers. r=adamgreig a=rcls Add the Cortex-M7 TCM and cache access control registers. These are documented in the Cortex-M7 generic user guide (ARM DUI 0646C). I'm not sure what feature gate these should be on - should I add a new one for Cortex-M7? Currently I have them on `not(armv6m)` - they do not appear to be in the ARMv7M architecture documentation, so I presume they are M7 specific. Co-authored-by: Ralph Loader <ralph1loader@gmail.com>
2021-09-06Add the Cortex-M7 TCM and cache access control registers.Gravatar Ralph Loader 2-0/+124
These registers appear to specific to the Cortex-M7, so add a feature gate "cm7".
2021-09-05Merge #339Gravatar bors[bot] 1-1/+1
339: Fix AIRCR PRIGROUP mask r=thejpster a=msamsonoff Closes #338 Co-authored-by: Matthew W. Samsonoff <matt.samsonoff@gmail.com>
2021-08-30Replace URL-relative doc links with intra-doc linksGravatar Alex Martens 2-2/+2
2021-08-29remove deprecated impl for Nr traitGravatar Marcel Hellwig 1-10/+1
2021-08-14Add DWT.set_cycle_countGravatar Alex Martens 1-0/+7
2021-08-14Deprecate get_cycle_count in favor of cycle_countGravatar Alex Martens 2-2/+13
This follows the rust C-GETTER API guidelines.
2021-08-08Add support for additional DWT countersGravatar Alex Martens 1-1/+154
This adds support for these counters: * CPI counter * Exception overhead counter * LSU counter * Folded-instruction counter
2021-08-05Fix slightly misleading examples.Gravatar Alex Martens 1-1/+3
2021-07-25Add pre-requisites for enabling the cycle counter to docsGravatar Alex Martens 1-0/+7
2021-06-12Update src/delay.rsGravatar David O'Connor 1-0/+1
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2021-06-12Use from instead of asGravatar David O'Connor 1-5/+5
2021-06-12remove inline on delay_us, and made u32 conversion syntax consistentGravatar David O'Connor 1-5/+4
2021-06-12Use . syntax instead of :: on delay_msGravatar David O'Connor 1-4/+4
2021-06-12Use overflow-workaround on delay_msGravatar David O'Connor 1-7/+9
2021-06-12Remove dependence on embedded-hal for DelayGravatar David O'Connor 1-10/+16
2021-05-05itm, dwt: limit some bitfields to u8Gravatar Viktor Sonesten 2-4/+4
2021-05-05tpiu: fix flipped SWOSupports field, reimplement with bitfieldGravatar Viktor Sonesten 1-11/+30
2021-05-05itm: impl functions related to trace generationGravatar Viktor Sonesten 1-1/+123
2021-05-05dwt: reimplement with bitfieldGravatar Viktor Sonesten 1-76/+65
2021-04-30dcb: add note about vendor-specific trace optionsGravatar Viktor Sonesten 1-0/+4
2021-04-30dwt: add missing #[inline]Gravatar Viktor Sonesten 1-0/+1
2021-04-30dwt: configure address comparison using structGravatar Viktor Sonesten 1-0/+143
2021-04-30tpiu: fix always-zero field-comparisonGravatar Viktor Sonesten 1-3/+3
2021-04-28dwt: impl functions related to trace generationGravatar Viktor Sonesten 1-0/+28
2021-04-28tpiu: impl functions related to trace data outputGravatar Viktor Sonesten 1-0/+70
2021-04-25Update warning about linker-plugin-lto not working with -Os/-OzGravatar Rahix 1-2/+2
This was fixed in rust 1.49 already, fortunately. But as the MSRV is still 1.38 we cannot drop the warning entirely yet.
2021-04-19Fix AIRCR PRIGROUP maskGravatar Matthew W. Samsonoff 1-1/+1
2021-03-19Compile the `mpu::RegisterBlock` struct on all targetsGravatar dimpolo 1-1/+1
closes https://github.com/rust-embedded/cortex-m/issues/336
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-07 23:09:31 +0000