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2023-03-01Add rtic-timer (timerqueue + monotonic) and rtic-monotonics (systick-monotonic)Gravatar Emil Fresk 1-324/+0
2023-03-01More work on new spawn/executorGravatar Emil Fresk 1-23/+2
2023-03-01New executor designGravatar Emil Fresk 1-67/+1
2023-03-01Start CI, disable docs buildingGravatar Emil Fresk 1-1/+1
2023-03-01Clippy fixesGravatar Emil Fresk 1-2/+2
2023-03-01Fix locks, basepri writeback errorGravatar Emil Fresk 1-1/+1
2023-03-01export Cell removed, expmples updatedGravatar Per Lindgren 1-4/+1
2023-03-01Removed Priority, simplified lifetime handlingGravatar Emil Fresk 1-78/+25
2023-03-01More removalGravatar Emil Fresk 1-5/+0
2023-03-01Even more cleanupGravatar Emil Fresk 1-70/+0
2023-03-01Old xtask test passGravatar Emil Fresk 1-4/+130
2022-07-27Remove use of basepri register on thumbv8m.baseGravatar David Watson 1-41/+104
The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-06-07fix ci: use SYST::PTRGravatar Jorge Aparicio 1-2/+2
SYST::ptr has been deprecated in cortex-m v0.7.5 SYST::PTR is available since cortex-m v0.7.0
2022-05-24Fix clash with defmtGravatar Emil Fresk 1-1/+3
2022-04-20Added check for resource usage and to generate an compile error for thumbv6 ↵Gravatar Emil Fresk 1-0/+10
exceptions
2022-04-20Masks take 3Gravatar Emil Fresk 1-0/+24
2022-03-02Added support for SRP based scheduling for armv6mGravatar Per Lindgren 1-13/+135
2022-02-22Clippy with pedantic suggestionsGravatar Henrik Tjäder 1-3/+5
2021-12-14Idle: Switch to NOP instead of WFIGravatar Henrik Tjäder 1-0/+1
Add example how to get old WFI behaviour
2021-09-28Fix export of SYSTGravatar Emil Fresk 1-1/+1
2021-09-14Cleanup export and actually use rtic::export, made fn init inlineGravatar Emil Fresk 1-3/+4
2021-08-16Remove linked list impl - use heapless, linked list init now const fnGravatar Emil Fresk 1-0/+1
2021-07-09const genericsGravatar Andrey Zgarbul 1-5/+4
2021-02-18Now with new monotonic trait and crateGravatar Emil Fresk 1-2/+2
2020-12-12Monotonic codegen now passing compile stageGravatar Emil Fresk 1-1/+1
2020-12-10More workGravatar Emil Fresk 1-0/+8
2020-12-08TQ handlers being generatedGravatar Emil Fresk 1-1/+1
2020-12-03Save, init generation fixedGravatar Emil Fresk 1-1/+1
2020-10-15Implement all clippy suggestionsGravatar Henrik Tjäder 1-0/+21
2020-10-01Remove exports related to heterogeneous multi-core supportGravatar Henrik Tjäder 1-2/+0
2020-10-01Added `bare_metal::CriticalSection` to `init::Context`Gravatar Emil Fresk 1-0/+1
2020-09-01Remove stale code, fix comment stylingGravatar Henrik Tjäder 1-2/+2
2020-09-01Brutally yank out multicoreGravatar Henrik Tjäder 1-10/+1
2020-06-11Rename RTFM to RTICGravatar Henrik Tjäder 1-1/+1
2019-09-15don't use deprecated APIGravatar Jorge Aparicio 1-1/+1
2019-06-24Monotonic trait is safe; add MultiCore traitGravatar Jorge Aparicio 1-0/+7
2019-06-13rtfm-syntax refactor + heterogeneous multi-core supportGravatar Jorge Aparicio 1-15/+41
2019-05-21bump heapless dependency to v0.5.0; remove "nightly" featureGravatar Jorge Aparicio 1-2/+2
with the upcoming version of heapless we are able to initialize all internal queues in const context removing the need for late initialization this commit also removes the "nightly" feature because all the optimization provided by it are now enabled by default
2019-05-21removes the maybe_uninit feature gateGravatar Jorge Aparicio 1-30/+0
and stop newtyping `core::mem::MaybeUninit`
2019-05-01implement RFCs 147 and 155, etc.Gravatar Jorge Aparicio 1-83/+30
This commit: - Implements RFC 147: "all functions must be safe" - Implements RFC 155: "explicit Context parameter" - Implements the pending breaking change #141: reject assign syntax in `init` (which was used to initialize late resources) - Refactors code generation to make it more readable -- there are no more random identifiers in the output -- and align it with the book description of RTFM internals. - Makes the framework hard depend on `core::mem::MaybeUninit` and thus will require nightly until that API is stabilized. - Fixes a ceiling analysis bug where the priority of the system timer was not considered in the analysis. - Shrinks the size of all the internal queues by turning `AtomicUsize` indices into `AtomicU8`s. - Removes the integration with `owned_singleton`.
2019-04-16more nightly fixesGravatar Jorge Aparicio 1-3/+3
2019-04-16[NFC] fix nightly ciGravatar Jorge Aparicio 1-3/+3
2019-02-19turn all potential UB into panicsGravatar Jorge Aparicio 1-30/+8
2019-02-19add "nightly" featureGravatar Jorge Aparicio 1-4/+61
2019-02-16cargo fmtGravatar Jorge Aparicio 1-1/+3
2019-02-16make debug builds reproducibleGravatar Jorge Aparicio 1-2/+25
2018-12-16properly handle #[cfg] (conditional compilation) on resourcesGravatar Jorge Aparicio 1-1/+0
2018-12-16use the single core variant of spsc::QueueGravatar Jorge Aparicio 1-3/+3
2018-11-04impl Mutex on all shared resourcesGravatar Jorge Aparicio 1-5/+84
document how to write generic code that operates on resources
2018-11-03v0.4.0Gravatar Jorge Aparicio 1-0/+84
closes #32 closes #33
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