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2020-07-21Add new InterruptNumber traitGravatar Adam Greig 2-34/+53
2020-07-18Merge #247Gravatar bors[bot] 2-9/+9
2020-07-18Correct typo in RASR register aliasesGravatar R. Kyle Murphy 2-9/+9
2020-07-16Merge #246Gravatar bors[bot] 1-1/+1
2020-07-16Always link pre-built asm, required for new cache management functionsGravatar Adam Greig 1-1/+1
2020-07-14Merge #244Gravatar bors[bot] 1-1/+1
2020-07-14Updated repository URL in 'Cargo.toml' fileGravatar Vincent Esche 1-1/+1
2020-07-12Merge #243Gravatar bors[bot] 1-3/+6
2020-07-12Allow the taken flag to be optimized outGravatar Jonas Schievink 1-3/+6
2020-07-08Merge #240Gravatar bors[bot] 1-4/+7
2020-07-09Expand iff and reword last sentenceGravatar Daniel Egger 1-2/+2
2020-07-09Change spelling of initialisation to AEGravatar Daniel Egger 1-1/+1
2020-07-09Update src/asm.rsGravatar Daniel Egger 1-1/+1
2020-07-09Better delay descriptionGravatar Daniel Egger 1-4/+7
2020-07-05Merge pull request #205 from hug-dev/enable-exceptionsGravatar Daniel Egger 1-0/+75
2020-07-05Merge #234Gravatar bors[bot] 9-8/+53
2020-07-05Use assembly sequences to enable caches.Gravatar Cliff L. Biffle 9-8/+53
2020-06-24Add a function to get SHCSR enable bit positionsGravatar Hugues de Valon 1-47/+28
2020-06-19Merge #231Gravatar bors[bot] 1-1/+1
2020-06-19Correct the documentation for the `SCB::set_pendst` functionGravatar Peter Taylor 1-1/+1
2020-06-11Merge #220Gravatar bors[bot] 11-3/+378
2020-06-11Update assemble.shGravatar Dániel Buga 1-1/+1
2020-06-10Merge #225 #226Gravatar bors[bot] 3-2/+113
2020-06-10Merge #227Gravatar bors[bot] 1-1/+12
2020-06-09ITM: don't test reserved bits in is_fifo_readyGravatar Cliff L. Biffle 1-1/+12
2020-06-09Expose the orphaned ICTR/ACTLR registers.Gravatar Cliff L. Biffle 2-1/+77
2020-06-09Initial ARMv8-M MPU support.Gravatar Cliff L. Biffle 1-1/+36
2020-06-06Add #[allow(clippy::missing_inline_in_public_items)] for consistencyGravatar Dániel Buga 1-0/+1
2020-06-06Make RMode methods actually accessibleGravatar Dániel Buga 1-4/+4
2020-06-06Add missing #[inline]sGravatar Dániel Buga 1-0/+14
2020-06-06Oops. Fix pattern matchingGravatar Dániel Buga 1-4/+4
2020-06-06Add methods to RModeGravatar Dániel Buga 1-13/+39
2020-06-06Implement bit manipulation methodsGravatar Dániel Buga 1-0/+128
2020-06-06Merge #222Gravatar bors[bot] 1-0/+1
2020-06-06Fix clippy warningGravatar Dániel Buga 1-0/+1
2020-05-28Stylistic updates, add from_bitsGravatar Dániel Buga 1-11/+17
2020-05-28Fix remaining compiler sadnessGravatar Dániel Buga 1-5/+9
2020-05-28Where did those ifs come from...Gravatar Dániel Buga 1-9/+9
2020-05-28Fix doc commentsGravatar Dániel Buga 1-15/+15
2020-05-28Update blobsGravatar Dániel Buga 8-3/+4
2020-05-28Fix store instructionsGravatar Dániel Buga 2-2/+2
2020-05-27Add missing EOLGravatar Dániel Buga 1-1/+1
2020-05-27Add new assembly file to assembler scriptGravatar Dániel Buga 1-3/+6
2020-05-27Add doc commentsGravatar Dániel Buga 1-0/+12
2020-05-27Implement accessing FPSCRGravatar Dániel Buga 3-0/+180
2020-05-25Merge #219Gravatar bors[bot] 1-1/+1
2020-05-24ITM: don't test reserved bits in is_fifo_readyGravatar Cliff L. Biffle 1-1/+1
2020-05-19Merge #218Gravatar bors[bot] 1-1/+1
2020-05-19Fix changelog linkGravatar Vadim Kaushan 1-1/+1
2020-05-17Merge #207Gravatar bors[bot] 1-0/+4