Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2020-07-18 | Correct typo in RASR register aliases | 1 | -3/+3 | |
2019-07-29 | Update for 2018 edition | 1 | -11/+11 | |
2019-03-12 | Merge #106 | 1 | -0/+2 | |
2019-03-12 | Merge #127 | 1 | -0/+8 | |
2019-03-12 | Fix rebase syntax error; disable STIR test on armv6m | 1 | -0/+1 | |
2019-03-12 | Add STIR register address test | 1 | -0/+1 | |
2018-12-15 | Test fixes | 1 | -0/+8 | |
2018-07-13 | Rename `shcrs` to `shcsr` in `scb::RegisterBlock` | 1 | -1/+1 | |
2018-05-11 | fix x86_64 tests | 1 | -2/+2 | |
2017-12-23 | revise peripheral API | 1 | -2/+0 | |
2017-12-18 | Make all available NVIC registers accessible | 1 | -6/+0 | |
2017-12-09 | fix tests | 1 | -11/+11 | |
2017-08-05 | add Formatter and Flush Control Register to struct TPIU | 1 | -0/+1 | |
2017-03-07 | revamp for memory safety | 1 | -119/+124 | |
2016-09-27 | initial commit | 1 | -0/+162 |