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2020-07-21Add new InterruptNumber traitGravatar Adam Greig 2-34/+53
2020-07-18Merge #247Gravatar bors[bot] 2-9/+9
247: Correct typo in RASR register aliases r=adamgreig a=orclev Fixes the typo in the a1, a2, and a3 aliases of the RASR MPU register. Co-authored-by: R. Kyle Murphy <orclev@gmail.com>
2020-07-18Correct typo in RASR register aliasesGravatar R. Kyle Murphy 2-9/+9
Fixes the typo in the a1, a2, and a3 aliases of the RASR MPU register.
2020-07-16Merge #246Gravatar bors[bot] 1-1/+1
246: Always link pre-built asm, required for new cache management functions r=therealprof a=adamgreig In #234 we added new `__enable_icache` and `__enable_dcache` assembly routines, but without providing an inline assembly version, to reduce duplication and since there wasn't an expected performance impact. However, our build.rs currently only links the pre-built object if the `inline-asm` feature is disabled, which means currently you can't call `enable_icache()` and use `inline-asm` at the same time. This PR makes us always link against the pre-built objects (for thumb targets) even if `inline-asm` is used; the pre-built object would only be used for the cache management routines at present but we may want to put more routines into the assembly blob only in the future. Closes #245. Co-authored-by: Adam Greig <adam@adamgreig.com>
2020-07-16Always link pre-built asm, required for new cache management functionsGravatar Adam Greig 1-1/+1
2020-07-14Merge #244Gravatar bors[bot] 1-1/+1
244: Updated repository URL in 'Cargo.toml' file r=adamgreig a=regexident Co-authored-by: Vincent Esche <138017+regexident@users.noreply.github.com>
2020-07-14Updated repository URL in 'Cargo.toml' fileGravatar Vincent Esche 1-1/+1
2020-07-12Merge #243Gravatar bors[bot] 1-3/+6
243: Allow the taken flag to be optimized out r=adamgreig a=jonas-schievink Fixes https://github.com/rust-embedded/cortex-m/issues/242 Verified manually that it still prevents linking in multiple versions. Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-07-12Allow the taken flag to be optimized outGravatar Jonas Schievink 1-3/+6
2020-07-08Merge #240Gravatar bors[bot] 1-4/+7
240: Better delay description r=jonas-schievink a=therealprof CC #236 Signed-off-by: Daniel Egger <daniel@eggers-club.de> Co-authored-by: Daniel Egger <daniel@eggers-club.de>
2020-07-09Expand iff and reword last sentenceGravatar Daniel Egger 1-2/+2
Signed-off-by: Daniel Egger <daniel@eggers-club.de>
2020-07-09Change spelling of initialisation to AEGravatar Daniel Egger 1-1/+1
Signed-off-by: Daniel Egger <daniel@eggers-club.de>
2020-07-09Update src/asm.rsGravatar Daniel Egger 1-1/+1
Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>
2020-07-09Better delay descriptionGravatar Daniel Egger 1-4/+7
CC #236 Signed-off-by: Daniel Egger <daniel@eggers-club.de>
2020-07-05Merge pull request #205 from hug-dev/enable-exceptionsGravatar Daniel Egger 1-0/+75
Add SCB methods to enable/disable exceptions
2020-07-05Merge #234Gravatar bors[bot] 9-8/+53
234: Use assembly sequences to enable caches. r=adamgreig a=cbiffle See #232, which this partially fixes -- there's still the question of taking an interrupt in the midst of these sequences. Co-authored-by: Cliff L. Biffle <cliff@oxide.computer>
2020-07-05Use assembly sequences to enable caches.Gravatar Cliff L. Biffle 9-8/+53
See #232, which this partially fixes -- there's still the question of taking an interrupt in the midst of these sequences.
2020-06-24Add a function to get SHCSR enable bit positionsGravatar Hugues de Valon 1-47/+28
This removes the duplication of the look-up table and enforces some safety checks with the match statement. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
2020-06-19Merge #231Gravatar bors[bot] 1-1/+1
231: Correct the documentation for the `SCB::set_pendst` function r=jonas-schievink a=PTaylor-FluenTech Co-authored-by: Peter Taylor <PTaylor@FluenTech.info>
2020-06-19Correct the documentation for the `SCB::set_pendst` functionGravatar Peter Taylor 1-1/+1
2020-06-11Merge #220Gravatar bors[bot] 11-3/+378
220: Implement accessing FPSCR r=adamgreig a=bugadani On the nRF52, sometimes it is necessary to manipulate the FPSCR register, otherwise the device wakes up immediately from sleep. (At least on this device) the FPSCR is only available through `vmrs` instructions. I've implemented reading the register, parsing its bits and writing a raw value to the register, but let me know if I should also implement manipulation of the named bits. I would also like to request some assistance to get this to actually build, it's not clear to me how `.s` files are compiled in this library. I'm also not certain where the actual place for this would be - in the registers, or in the `fpu` module. Co-authored-by: Dániel Buga <bugadani@gmail.com> Co-authored-by: Dániel Buga <daniel@revolutionrobotics.org>
2020-06-11Update assemble.shGravatar Dániel Buga 1-1/+1
Co-authored-by: Adam Greig <adam@adamgreig.com>
2020-06-10Merge #225 #226Gravatar bors[bot] 3-2/+113
225: Initial ARMv8-M MPU support. r=adamgreig a=cbiffle The v8-M MPU is entirely different from, and incompatible with, the earlier PMSA MPU. And so this commit does two things: 1. Makes the old RegisterBlock depend on armv6m (for M0+) and armv7m. 2. Defines a new RegisterBlock containing the right layout for v8m. The hack for documenting fields by opting in x86-64 means the v8m version won't appear in the docs. 226: Expose the orphaned ICTR/ACTLR registers. r=adamgreig a=cbiffle In ARMv7-M these were floating alone in system control space, without a unifying name. As a result, they weren't exposed in earlier versions of this crate. In ARMv8-M they have been given a name, the Implementation Control Block, and more registers have been added. I've used that name for all architecture revisions. Co-authored-by: Cliff L. Biffle <cliff@oxide.computer>
2020-06-10Merge #227Gravatar bors[bot] 1-1/+12
227: ITM: don't test reserved bits in is_fifo_ready r=adamgreig a=bcantrill This is a follow up to the discussion in #219, capturing the conclusion by @cbiffle and @adamgreig there: to indicate that the ITM FIFO is ready on FIFOREADY (only) on ARMv7-M (only) and to indicate the FIFI is ready on *either* FIFOREADY *or* DISABLED on ARMv8-M. ITM has been tested and verified on an ARMv7-M CPU (an STM32F407, a Cortex-M4) and an ARMv8-M CPU (an LPC55S69, a Cortex-M33). Without this fix, any use of ITM will hang on ARMv8-M -- which may in fact be the root cause of #74... Co-authored-by: Cliff L. Biffle <cliff@oxide.computer>
2020-06-09ITM: don't test reserved bits in is_fifo_readyGravatar Cliff L. Biffle 1-1/+12
On ARMv7-M, bits 31:1 of the value read from STIMx are reserved, so comparing them against zero is a bad idea. On ARMv8-M, bit 1 has been repurposed to indicate DISABLED. This means that the is_fifo_ready impl hangs forever when ITM is disabled on a Cortex-M33 (for example). Changed to test only the FIFOREADY bit on ARMv7-M, and to test either FIFOREADY or DISABLED on ARMv8-M.
2020-06-09Expose the orphaned ICTR/ACTLR registers.Gravatar Cliff L. Biffle 2-1/+77
In ARMv7-M these were floating alone in system control space, without a unifying name. As a result, they weren't exposed in earlier versions of this crate. In ARMv8-M they have been given a name, the Implementation Control Block, and more registers have been added. I've used that name for all architecture revisions.
2020-06-09Initial ARMv8-M MPU support.Gravatar Cliff L. Biffle 1-1/+36
The v8-M MPU is entirely different from, and incompatible with, the earlier PMSA MPU. And so this commit does two things: 1. Makes the old RegisterBlock depend on armv6m (for M0+) and armv7m. 2. Defines a new RegisterBlock containing the right layout for v8m. The hack for documenting fields by opting in x86-64 means the v8m version won't appear in the docs.
2020-06-06Add #[allow(clippy::missing_inline_in_public_items)] for consistencyGravatar Dániel Buga 1-0/+1
2020-06-06Make RMode methods actually accessibleGravatar Dániel Buga 1-4/+4
2020-06-06Add missing #[inline]sGravatar Dániel Buga 1-0/+14
2020-06-06Oops. Fix pattern matchingGravatar Dániel Buga 1-4/+4
2020-06-06Add methods to RModeGravatar Dániel Buga 1-13/+39
2020-06-06Implement bit manipulation methodsGravatar Dániel Buga 1-0/+128
2020-06-06Merge #222Gravatar bors[bot] 1-0/+1
222: Fix clippy warning r=adamgreig a=bugadani Explicitly allow manual non-exhaustive violations Co-authored-by: Dániel Buga <daniel@revolutionrobotics.org>
2020-06-06Fix clippy warningGravatar Dániel Buga 1-0/+1
2020-05-28Stylistic updates, add from_bitsGravatar Dániel Buga 1-11/+17
2020-05-28Fix remaining compiler sadnessGravatar Dániel Buga 1-5/+9
2020-05-28Where did those ifs come from...Gravatar Dániel Buga 1-9/+9
2020-05-28Fix doc commentsGravatar Dániel Buga 1-15/+15
2020-05-28Update blobsGravatar Dániel Buga 8-3/+4
2020-05-28Fix store instructionsGravatar Dániel Buga 2-2/+2
2020-05-27Add missing EOLGravatar Dániel Buga 1-1/+1
2020-05-27Add new assembly file to assembler scriptGravatar Dániel Buga 1-3/+6
2020-05-27Add doc commentsGravatar Dániel Buga 1-0/+12
2020-05-27Implement accessing FPSCRGravatar Dániel Buga 3-0/+180
2020-05-25Merge #219Gravatar bors[bot] 1-1/+1
219: ITM: don't test reserved bits in is_fifo_ready r=adamgreig a=cbiffle On ARMv7-M, bits 31:1 of the value read from STIMx are reserved, so comparing them against zero is a bad idea. On ARMv8-M, bit 1 has been repurposed to indicate DISABLED. This means that the is_fifo_ready impl hangs forever when ITM is disabled on a Cortex-M33 (for example). Changed to test only the FIFOREADY bit. @bcantrill Co-authored-by: Cliff L. Biffle <cliff@oxide.computer>
2020-05-24ITM: don't test reserved bits in is_fifo_readyGravatar Cliff L. Biffle 1-1/+1
On ARMv7-M, bits 31:1 of the value read from STIMx are reserved, so comparing them against zero is a bad idea. On ARMv8-M, bit 1 has been repurposed to indicate DISABLED. This means that the is_fifo_ready impl hangs forever when ITM is disabled on a Cortex-M33 (for example). Changed to test only the FIFOREADY bit.
2020-05-19Merge #218Gravatar bors[bot] 1-1/+1
218: Fix changelog link r=jonas-schievink a=Disasm Co-authored-by: Vadim Kaushan <admin@disasm.info>
2020-05-19Fix changelog linkGravatar Vadim Kaushan 1-1/+1
2020-05-17Merge #207Gravatar bors[bot] 1-0/+4
207: Add MSRV note to README r=therealprof a=adamgreig Ref. https://github.com/rust-embedded/wg/issues/445 Co-authored-by: Adam Greig <adam@adamgreig.com>
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