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2019-07-29Fix missing `crate::`Gravatar Adam Greig 2-2/+2
2019-07-29Update for 2018 editionGravatar Adam Greig 13-70/+59
2019-07-24Define MSRV to be 1.31.0 and unconditionally use const-fnGravatar Adam Greig 1-4/+3
2019-06-19add NVIC::{mask,unmask}Gravatar Jorge Aparicio 1-5/+26
these are the "static method" (methods that don't take `self`) versions of NVIC::{enable,disable} in the same vein as the existing NVIC::{pend,unpend} this commit also deprecates the existing NVIC::{enable,disable} methods and notes that NVIC::enable is unsound because it should be an `unsafe` method (like interrupt::enable and basepri::write, it can break critical sections) but it's marked as safe. Its replacement, NVIC::unmask, has the correct unsafety setting: it's an `unsafe` function.
2019-06-13Remove debug_assert from Peripherals::stealGravatar Matti Virkkunen 1-2/+0
2019-04-24Derive Debug, PartialEq and Eq for more typesGravatar Jonas Schievink 3-2/+3
2019-04-14Merge #138Gravatar bors[bot] 1-0/+20
138: scb: add static version of system_reset as sys_reset r=korken89 a=hdhoang As suggested in https://github.com/ah-/anne-key/pull/94. I branched this off v0.5.8 to verify the function in that PR, and against rtfm v0.3 in https://github.com/hdhoang/anne-key/commit/d6fb831cbbb46bc10a6184b78bf13e00245234d6 I have cloned the body of `system_reset`, do you think we should call one from the other (e.g. ignoring `self` in `system_reset`, or stealing `Peripherals` in `system_reset2`)? Co-authored-by: Hoàng Đức Hiếu <code@hdhoang.space>
2019-04-13deprecate system_reset in favor of static sys_resetGravatar Hoàng Đức Hiếu 1-3/+2
2019-03-21scb: add static version of system_reset as system_reset2Gravatar Hoàng Đức Hiếu 1-0/+21
2019-03-12Merge #106Gravatar bors[bot] 3-6/+54
106: Stir register and debugger check r=adamgreig a=thenewwazoo Adds support for requesting an interrupt via the STIR register and checking whether a debugger is attached. Co-authored-by: Brandon Matthews <bmatthews@zipcar.com> Co-authored-by: Brandon Matthews <bmatthews@optimaltour.us>
2019-03-12Merge #127Gravatar bors[bot] 2-1/+29
127: Cortex M0(+) DWT fixes r=adamgreig a=korken89 The current DWT setup has a lot of registers that are not available in Cortex-M0(+), fixes are added here. Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2019-03-12Fix STIR register test, remove armv6m-related offsets in NVICGravatar Brandon Matthews 1-5/+2
2019-03-12Merge #97Gravatar bors[bot] 2-2/+2
97: Rename `shcrs` to `shcsr` in `scb::RegisterBlock` r=adamgreig a=rajivr Commit `c290aa4e` introduced `shcrs` field to `scb::RegisterBlock`. In CMSIS, this field is `shcsr`. https://github.com/ARM-software/CMSIS_5/blob/5.3.0/CMSIS/Core/Include/core_cm4.h#L449 This patch changes `shcrs` to `shcsr`. Signed-off-by: Rajiv Ranganath <rajiv.ranganath@gmail.com> Co-authored-by: Rajiv Ranganath <rajiv.ranganath@gmail.com>
2019-03-12Update is_debugger_attached so as not to clear S_RESET_ST and S_RETIRE_STGravatar Brandon Matthews 1-8/+14
2019-03-12Fix rebase syntax error; disable STIR test on armv6mGravatar Brandon Matthews 2-0/+2
2019-03-12Expand is_debugger_attached noteGravatar Brandon Matthews 1-2/+5
2019-03-12Add explanatory note about C_DEBUGENGravatar Brandon Matthews 1-3/+9
2019-03-12Add note that NVIC::request is not available on armv6mGravatar Brandon Matthews 1-0/+2
2019-03-12Exclude unused import and elide nvic::request for armv6mGravatar Brandon Matthews 1-2/+3
2019-03-12Add STIR register address testGravatar Brandon Matthews 1-0/+1
2019-03-12Add support for debugger checkGravatar Brandon Matthews 1-2/+6
2019-03-12Add STIR register to NVIC peripheralGravatar Brandon Matthews 1-1/+27
2018-12-15Fix for error in TravisGravatar Emil Fresk 1-1/+3
2018-12-15Test fixesGravatar Emil Fresk 1-0/+8
2018-12-15Fixes for DWT on Cortex-M0Gravatar Emil Fresk 1-0/+18
2018-12-09Upgrade to aligned 0.3Gravatar Raphael Nestler 1-3/+3
2018-11-20Add api to set SLEEPONEXIT bit in SCR registerGravatar Simon Vandel Sillesen 1-0/+18
2018-10-27deprecate NVIC.{clear,set}_pending in favor of NVIC::{un,}pendGravatar Jorge Aparicio 1-5/+25
NVIC::{un,}pend are static methods that don't require an instance of NVIC to be invoked.
2018-10-26deny warnings only on nightlyGravatar Jorge Aparicio 1-1/+0
lints have changed between nightly and stable
2018-10-26remove hidden variantGravatar Jorge Aparicio 1-5/+0
it was there to maybe support adding DebugMonitor in the future but it has already been added
2018-10-26add DebugMonitor variant to SystemHandlerGravatar Jorge Aparicio 1-2/+6
2018-10-26fix shiftGravatar Jorge Aparicio 1-2/+2
2018-10-24fix warningGravatar Jorge Aparicio 1-1/+0
2018-10-24add high level API to set priority of system handlersGravatar Jorge Aparicio 2-0/+118
2018-10-01Autoformat scb.rs by rustfmtGravatar qwerty19106 1-13/+14
2018-10-01Remove blank lineGravatar qwerty19106 1-1/+0
2018-10-01Fix function names and remove exclusive accessGravatar qwerty19106 1-3/+3
2018-09-24Fix duplicate PendSV.Gravatar qwerty19106 1-56/+28
2018-09-24Added Pending SV (Service Call) and SysTick flagsGravatar qwerty19106 1-0/+56
2018-09-09Merge #112Gravatar bors[bot] 1-0/+26
112: Add PendSV exception set and clear to SCB r=adamgreig a=ekohandel This change adds the ability to easily set, clear, and inquire the status of the PendSV exception via the SCB peripheral on all Cortex-M platforms. Co-authored-by: Abe Kohandel <e.kohandel@gmail.com>
2018-09-06make `iprintln!` not depend on `iprint!`Gravatar Jorge Aparicio 1-3/+3
the preferred way to import macros in Rust 2018 is via `use`. If you import `iprintln` and try to use you'll get an error if the `iprint` macro has not been imported as well. This commit makes `iprintln` work w/o having to import `iprint` as well.
2018-09-06Rename BIT_TRCENA to DCB_DEMCR_TRCENA, replace 0x01 with 1Gravatar Michael Watzko 1-3/+3
2018-09-05Fix typoGravatar Michael Watzko 1-5/+5
2018-09-05Move the whole shift to the constantGravatar Michael Watzko 1-3/+3
2018-09-05Move shift-constant 24 to BIT_TRACENAGravatar Michael Watzko 1-2/+4
2018-09-03Add PendSV exception set and clear to SCBGravatar Abe Kohandel 1-0/+26
2018-09-02Be more verbose about the bit being set / resetGravatar kellerkindt 1-2/+4
2018-09-02Add DCB::enable_trace() and DCB::disable_trace()Gravatar kellerkindt 1-0/+17
2018-08-27v0.5.5Gravatar Jorge Aparicio 1-8/+1
2018-08-26remove build dependency on arm-none-eabi-gccGravatar Jorge Aparicio 2-9/+33
by shipping pre-assembled object files. This is the same approach as the one used in rust-embedded/cortex-m#95
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